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[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Diff between revs 71 and 90

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Rev 71 Rev 90
Line 125... Line 125...
                                iword[17:14] };
                                iword[17:14] };
 
 
        // 0 LUTs
        // 0 LUTs
        assign  w_dcdA = w_dcdR;
        assign  w_dcdA = w_dcdR;
        // 2 LUTs, 1 delay each
        // 2 LUTs, 1 delay each
        assign  w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
        // assign       w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
        // 0 LUTs
        // 0 LUTs
        assign  w_dcdA_pc = w_dcdR_pc;
        assign  w_dcdA_pc = w_dcdR_pc;
        assign  w_dcdA_cc = w_dcdR_cc;
        assign  w_dcdA_cc = w_dcdR_cc;
        // 2 LUTs, 1 delays each
        // 2 LUTs, 1 delays each
Line 170... Line 170...
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
        assign  w_wR_n   = ((w_dcdM)&&(w_op[0]))
        assign  w_wR_n   = ((w_dcdM)&&(w_op[0]))
                                ||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
                                ||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
                                ||(w_cmptst);
                                ||(w_cmptst);
        assign  w_wR     = ~w_wR_n;
        assign  w_wR     = ~w_wR_n;
        // 1-output bit (5 Opcode bits, 3 out-reg bits, 3 condition bits)
        //
 
        // 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
        //      
        //      
        //      This'd be 4 LUTs, save that we have the carve out for NOOPs
        //      This'd be 4 LUTs, save that we have the carve out for NOOPs
 
        //      and writes to the PC/CC register(s).
        assign  w_wF     = (w_cmptst)
        assign  w_wF     = (w_cmptst)
                        ||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
                        ||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
                                ||((w_ALU)&&(~w_mov)&&(~w_ldixx))));
                                ||((w_ALU)&&(~w_mov)&&(~w_ldixx)
 
                                        &&(iword[30:28] != 3'h7))));
 
 
        // Bottom 13 bits: no LUT's
        // Bottom 13 bits: no LUT's
        // w_dcd[12: 0] -- no LUTs
        // w_dcd[12: 0] -- no LUTs
        // w_dcd[   13] -- 2 LUTs
        // w_dcd[   13] -- 2 LUTs
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
Line 332... Line 335...
        if (EARLY_BRANCHING!=0)
        if (EARLY_BRANCHING!=0)
        begin
        begin
                reg                     r_early_branch;
                reg                     r_early_branch;
                reg     [(AW-1):0]       r_branch_pc;
                reg     [(AW-1):0]       r_branch_pc;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if ((i_ce)&&(w_dcdR_pc)&&(w_cond[3]))
                if (i_ce)
                        begin
                        begin
                                if ((w_op == 5'hf)&&(w_dcdB_pc)&&(w_dcdA_pc))
                        if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
                                begin // Move (X+PC) to PC
                        begin
                                        r_early_branch     <= 1'b1;
                                if (w_op[4:1] == 4'hb) // LDI to PC
                                end else if (w_op[4:1] == 4'hb) // LDI to PC
 
                                begin // LDI x,PC
                                begin // LDI x,PC
                                        r_early_branch     <= 1'b1;
                                        r_early_branch     <= 1'b1;
                                end else if ((w_op[4:0] == 5'h00)&&(~w_rB)&&(w_dcdA_pc))
                                end else if ((w_op[4:0]==5'h02)&&(~iword[18]))
                                begin // Add x,PC
                                begin // Add x,PC
                                        r_early_branch     <= 1'b1;
                                        r_early_branch     <= 1'b1;
                                end else begin
                                end else begin
                                        r_early_branch     <= 1'b0;
                                        r_early_branch     <= 1'b0;
                                end
                                end
                        end else begin
                        end else
                                if (i_ce)
 
                                        r_early_branch <= 1'b0;
                                        r_early_branch <= 1'b0;
                        end
                        end
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_ce)
                        if (i_ce)
                        begin
                        begin
                                if (w_op[4:1] == 4'hb)
                                if (w_op[4:1] == 4'hb) // LDI
                                        r_branch_pc <= {{(AW-23){w_I[22]}},w_I};
                                        r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
                                else
                                else // Add x,PC
                                r_branch_pc <= i_pc+{{(AW-23){w_I[22]}},w_I}
                                r_branch_pc <= i_pc
 
                                        + {{(AW-18){iword[17]}},iword[16:0]}
                                                +{{(AW-1){1'b0}},1'b1};
                                                +{{(AW-1){1'b0}},1'b1};
                        end
                        end
 
 
                assign  o_early_branch     = r_early_branch;
                assign  o_early_branch     = r_early_branch;
                assign  o_branch_pc        = r_branch_pc;
                assign  o_branch_pc        = r_branch_pc;

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