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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Diff between revs 3 and 36

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Line 9... Line 9...
//      In the interests of code simplicity, this memory operator is 
//      In the interests of code simplicity, this memory operator is 
//      susceptible to unknown results should a new command be sent to it
//      susceptible to unknown results should a new command be sent to it
//      before it completes the last one.  Unpredictable results might then
//      before it completes the last one.  Unpredictable results might then
//      occurr.
//      occurr.
//
//
 
//      20150919 -- Added support for handling BUS ERR's (i.e., the WB
 
//              error signal).
 
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
Line 34... Line 37...
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
module  memops(i_clk, i_rst, i_stb,
module  memops(i_clk, i_rst, i_stb,
                i_op, i_addr, i_data, i_oreg,
                i_op, i_addr, i_data, i_oreg,
                        o_busy, o_valid, o_wreg, o_result,
                        o_busy, o_valid, o_err, o_wreg, o_result,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                i_wb_ack, i_wb_stall, i_wb_data);
                        o_wb_stb_gbl, o_wb_stb_lcl,
 
                        o_wb_we, o_wb_addr, o_wb_data,
 
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
        input                   i_clk, i_rst;
        input                   i_clk, i_rst;
        input                   i_stb;
        input                   i_stb;
        // CPU interface
        // CPU interface
        input                   i_op;
        input                   i_op;
        input           [31:0]   i_addr;
        input           [31:0]   i_addr;
        input           [31:0]   i_data;
        input           [31:0]   i_data;
        input           [4:0]    i_oreg;
        input           [4:0]    i_oreg;
        // CPU outputs
        // CPU outputs
        output  wire            o_busy;
        output  wire            o_busy;
        output  reg             o_valid;
        output  reg             o_valid;
 
        output  reg             o_err;
        output  reg     [4:0]    o_wreg;
        output  reg     [4:0]    o_wreg;
        output  reg     [31:0]   o_result;
        output  reg     [31:0]   o_result;
        // Wishbone outputs
        // Wishbone outputs
        output  reg             o_wb_cyc, o_wb_stb, o_wb_we;
        output  reg             o_wb_cyc_gbl, o_wb_stb_gbl;
 
        output  reg             o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
        output  reg     [31:0]   o_wb_addr, o_wb_data;
        output  reg     [31:0]   o_wb_addr, o_wb_data;
        // Wishbone inputs
        // Wishbone inputs
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 
 
        wire    gbl_stb, lcl_stb;
 
        assign  lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
 
        assign  gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        o_wb_cyc <= 1'b0;
                begin
                else if (o_wb_cyc)
                        o_wb_cyc_gbl <= 1'b0;
                        o_wb_cyc <= (~i_wb_ack);
                        o_wb_cyc_lcl <= 1'b0;
                else if (i_stb) // New memory operation
                end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
                        // Grab the wishbone
                begin
                        o_wb_cyc  <= 1'b1;
                        if ((i_wb_ack)||(i_wb_err))
 
                        begin
 
                                o_wb_cyc_gbl <= 1'b0;
 
                                o_wb_cyc_lcl <= 1'b0;
 
                        end
 
                end else if (i_stb) // New memory operation
 
                begin // Grab the wishbone
 
                        o_wb_cyc_lcl <= lcl_stb;
 
                        o_wb_cyc_gbl <= gbl_stb;
 
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (o_wb_cyc)
                if (o_wb_cyc_gbl)
                        o_wb_stb <= (o_wb_stb)&&(i_wb_stall);
                        o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
                else
                else
                        o_wb_stb  <= i_stb; // Grab wishbone on new operation
                        o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation
 
        always @(posedge i_clk)
 
                if (o_wb_cyc_lcl)
 
                        o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
 
                else
 
                        o_wb_stb_lcl  <= lcl_stb; // Grab wishbone on new operation
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stb)
                if (i_stb)
                begin
                begin
                        o_wb_we   <= i_op;
                        o_wb_we   <= i_op;
                        o_wb_data <= i_data;
                        o_wb_data <= i_data;
                        o_wb_addr <= i_addr;
                        o_wb_addr <= i_addr;
                end
                end
 
 
        initial o_valid = 1'b0;
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we);
                o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
        assign  o_busy = o_wb_cyc;
        initial o_err = 1'b0;
 
        always @(posedge i_clk)
 
                o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
 
        assign  o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stb)
                if (i_stb)
                        o_wreg    <= i_oreg;
                        o_wreg    <= i_oreg;
        always @(posedge i_clk)
        always @(posedge i_clk)

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