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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Diff between revs 36 and 48

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Rev 36 Rev 48
Line 42... Line 42...
                        o_busy, o_valid, o_err, o_wreg, o_result,
                        o_busy, o_valid, o_err, o_wreg, o_result,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                        o_wb_stb_gbl, o_wb_stb_lcl,
                        o_wb_stb_gbl, o_wb_stb_lcl,
                        o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_we, o_wb_addr, o_wb_data,
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
 
        parameter       ADDRESS_WIDTH=24, AW=ADDRESS_WIDTH;
        input                   i_clk, i_rst;
        input                   i_clk, i_rst;
        input                   i_stb;
        input                   i_stb;
        // CPU interface
        // CPU interface
        input                   i_op;
        input                   i_op;
        input           [31:0]   i_addr;
        input           [31:0]   i_addr;
Line 58... Line 59...
        output  reg     [4:0]    o_wreg;
        output  reg     [4:0]    o_wreg;
        output  reg     [31:0]   o_result;
        output  reg     [31:0]   o_result;
        // Wishbone outputs
        // Wishbone outputs
        output  reg             o_wb_cyc_gbl, o_wb_stb_gbl;
        output  reg             o_wb_cyc_gbl, o_wb_stb_gbl;
        output  reg             o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
        output  reg             o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
        output  reg     [31:0]   o_wb_addr, o_wb_data;
        output  reg     [(AW-1):0]       o_wb_addr;
 
        output  reg     [31:0]   o_wb_data;
        // Wishbone inputs
        // Wishbone inputs
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 
        wire    gbl_stb, lcl_stb;
        wire    gbl_stb, lcl_stb;
Line 99... Line 101...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stb)
                if (i_stb)
                begin
                begin
                        o_wb_we   <= i_op;
                        o_wb_we   <= i_op;
                        o_wb_data <= i_data;
                        o_wb_data <= i_data;
                        o_wb_addr <= i_addr;
                        o_wb_addr <= i_addr[(AW-1):0];
                end
                end
 
 
        initial o_valid = 1'b0;
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
                o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);

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