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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Diff between revs 48 and 69

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//
//
//      20150919 -- Added support for handling BUS ERR's (i.e., the WB
//      20150919 -- Added support for handling BUS ERR's (i.e., the WB
//              error signal).
//              error signal).
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
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//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
module  memops(i_clk, i_rst, i_stb,
module  memops(i_clk, i_rst, i_stb, i_lock,
                i_op, i_addr, i_data, i_oreg,
                i_op, i_addr, i_data, i_oreg,
                        o_busy, o_valid, o_err, o_wreg, o_result,
                        o_busy, o_valid, o_err, o_wreg, o_result,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                        o_wb_stb_gbl, o_wb_stb_lcl,
                        o_wb_stb_gbl, o_wb_stb_lcl,
                        o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_we, o_wb_addr, o_wb_data,
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
        parameter       ADDRESS_WIDTH=24, AW=ADDRESS_WIDTH;
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
        input                   i_clk, i_rst;
        input                   i_clk, i_rst;
        input                   i_stb;
        input                   i_stb, i_lock;
        // CPU interface
        // CPU interface
        input                   i_op;
        input                   i_op;
        input           [31:0]   i_addr;
        input           [31:0]   i_addr;
        input           [31:0]   i_data;
        input           [31:0]   i_data;
        input           [4:0]    i_oreg;
        input           [4:0]    i_oreg;
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        output  reg             o_valid;
        output  reg             o_valid;
        output  reg             o_err;
        output  reg             o_err;
        output  reg     [4:0]    o_wreg;
        output  reg     [4:0]    o_wreg;
        output  reg     [31:0]   o_result;
        output  reg     [31:0]   o_result;
        // Wishbone outputs
        // Wishbone outputs
        output  reg             o_wb_cyc_gbl, o_wb_stb_gbl;
        output  wire            o_wb_cyc_gbl;
        output  reg             o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
        output  reg             o_wb_stb_gbl;
 
        output  wire            o_wb_cyc_lcl;
 
        output  reg             o_wb_stb_lcl;
 
        output  reg             o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [31:0]   o_wb_data;
        output  reg     [31:0]   o_wb_data;
        // Wishbone inputs
        // Wishbone inputs
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 
 
        reg     r_wb_cyc_gbl, r_wb_cyc_lcl;
        wire    gbl_stb, lcl_stb;
        wire    gbl_stb, lcl_stb;
        assign  lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
        assign  lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
        assign  gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
        assign  gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
 
 
        initial r_wb_cyc_gbl = 1'b0;
 
        initial r_wb_cyc_lcl = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        o_wb_cyc_gbl <= 1'b0;
                        r_wb_cyc_gbl <= 1'b0;
                        o_wb_cyc_lcl <= 1'b0;
                        r_wb_cyc_lcl <= 1'b0;
                end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
                end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
                begin
                begin
                        if ((i_wb_ack)||(i_wb_err))
                        if ((i_wb_ack)||(i_wb_err))
                        begin
                        begin
                                o_wb_cyc_gbl <= 1'b0;
                                r_wb_cyc_gbl <= 1'b0;
                                o_wb_cyc_lcl <= 1'b0;
                                r_wb_cyc_lcl <= 1'b0;
                        end
                        end
                end else if (i_stb) // New memory operation
                end else if (i_stb) // New memory operation
                begin // Grab the wishbone
                begin // Grab the wishbone
                        o_wb_cyc_lcl <= lcl_stb;
                        r_wb_cyc_lcl <= lcl_stb;
                        o_wb_cyc_gbl <= gbl_stb;
                        r_wb_cyc_gbl <= gbl_stb;
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (o_wb_cyc_gbl)
                if (o_wb_cyc_gbl)
                        o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
                        o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
                else
                else
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                if (i_stb)
                if (i_stb)
                        o_wreg    <= i_oreg;
                        o_wreg    <= i_oreg;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_wb_ack)
                if (i_wb_ack)
                        o_result <= i_wb_data;
                        o_result <= i_wb_data;
 
 
 
        generate
 
        if (IMPLEMENT_LOCK != 0)
 
        begin
 
                reg     lock_gbl, lock_lcl;
 
 
 
                initial lock_gbl = 1'b0;
 
                initial lock_lcl = 1'b0;
 
 
 
                always @(posedge i_clk)
 
                begin
 
                        lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
 
                        lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
 
                end
 
 
 
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
 
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
 
        end else begin
 
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl);
 
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl);
 
        end endgenerate
endmodule
endmodule
 
 
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