| Line 89... |
Line 89... |
o_pc <= i_pc;
|
o_pc <= i_pc;
|
end
|
end
|
|
|
initial tagval = 0;
|
initial tagval = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})
|
// It may be possible to recover a clock once the cache line
|
&&(i_wb_ack)&&(~i_wb_err))
|
// has been filled, but our prior attempt to do so has lead
|
// Our tag value changes any time we finish reading a
|
// to a race condition, so we keep this logic simple.
|
// new cache line
|
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
|
tagval <= o_wb_addr[(AW-1):CW];
|
lastpc <= tags[i_pc[(CW-1):PW]];
|
else if ((i_stall_n)&&(~o_wb_cyc))
|
else
|
// Otherwise, as long as we're not reading new stuff,
|
tagval <= tags[lastpc[(CW-1):PW]];
|
// the tag line changes any time the pipeline steps
|
|
// forwards. Our purpose here is primarily just to
|
|
// catch sudden changes. The result is that walking
|
|
// from one cache line to the next will cost a clock.
|
|
tagval <= tags[i_pc[(CW-1):PW]];
|
|
|
|
// i_pc will only increment when everything else isn't stalled, thus
|
// i_pc will only increment when everything else isn't stalled, thus
|
// we can set it without worrying about that. Doing this enables
|
// we can set it without worrying about that. Doing this enables
|
// us to work in spite of stalls. For example, if the next address
|
// us to work in spite of stalls. For example, if the next address
|
// isn't valid, but the decoder is stalled, get the next address
|
// isn't valid, but the decoder is stalled, get the next address
|
| Line 200... |
Line 195... |
// VMask ... is a section loaded?
|
// VMask ... is a section loaded?
|
initial vmask = 0;
|
initial vmask = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_cache))
|
if ((i_rst)||(i_clear_cache))
|
vmask <= 0;
|
vmask <= 0;
|
else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
|
else begin
|
vmask[lastpc[(CW-1):PW]] <= 1'b0;
|
if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
|
else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
|
|
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
|
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
|
|
if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
|
|
vmask[lastpc[(CW-1):PW]] <= 1'b0;
|
|
end
|
|
|
reg illegal_valid;
|
reg illegal_valid;
|
initial illegal_cache = 0;
|
initial illegal_cache = 0;
|
initial illegal_valid = 0;
|
initial illegal_valid = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
