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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Diff between revs 69 and 71

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Rev 69 Rev 71
Line 98... Line 98...
        // us to work in spite of stalls.  For example, if the next address
        // us to work in spite of stalls.  For example, if the next address
        // isn't valid, but the decoder is stalled, get the next address
        // isn't valid, but the decoder is stalled, get the next address
        // anyway.
        // anyway.
        initial lastpc = 0;
        initial lastpc = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((r_v)||(i_clear_cache)||(i_new_pc))
                if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                        lastpc <= i_pc;
                        lastpc <= i_pc;
 
 
        initial lasttag = 0;
        initial lasttag = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                lasttag <= i_pc[(AW-1):PW];
                lasttag <= i_pc[(AW-1):PW];
Line 118... Line 118...
        reg     [1:0]    delay;
        reg     [1:0]    delay;
 
 
        initial delay = 2'h3;
        initial delay = 2'h3;
        initial r_v = 1'b0;
        initial r_v = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache)||(i_new_pc)||(r_v))
                if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
                begin
                begin
                        r_v <= r_v_from_pc;
                        r_v <= r_v_from_pc;
                        delay <= 2'h2;
                        delay <= 2'h2;
                end else begin
                end else if (~r_v) begin // Otherwise, r_v was true and we were
                        r_v <= r_v_from_last;
                        r_v <= r_v_from_last;   // stalled, hence only if ~r_v
                        if (o_wb_cyc)
                        if (o_wb_cyc)
                                delay <= 2'h2;
                                delay <= 2'h2;
                        else if (delay != 0)
                        else if (delay != 0)
                                delay <= delay - 1;
                                delay <= delay - 1;
                end
                end
Line 164... Line 164...
                        // else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
                        // else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
                        //      tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
                        //      tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
 
 
                end else if ((~r_v)&&(delay==0)
                end else if ((~r_v)&&(delay==0)
                        &&((tagval != lastpc[(AW-1):CW])
                        &&((tagval != lastpc[(AW-1):CW])
                                ||(~vmask[lastpc[(CW-1):PW]])))
                                ||(~vmask[lastpc[(CW-1):PW]]))
 
                        &&(~o_illegal))
                begin
                begin
                        o_wb_cyc  <= 1'b1;
                        o_wb_cyc  <= 1'b1;
                        o_wb_stb  <= 1'b1;
                        o_wb_stb  <= 1'b1;
                        o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
                        o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
                        rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
                        rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
Line 187... Line 188...
                else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
                else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
                        vmask[lastpc[(CW-1):PW]] <= 1'b0;
                        vmask[lastpc[(CW-1):PW]] <= 1'b0;
                else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
                else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
                        vmask[rdaddr[(CW-1):PW]] <= 1'b1;
                        vmask[rdaddr[(CW-1):PW]] <= 1'b1;
 
 
 
        reg     illegal_valid;
        initial illegal_cache = 0;
        initial illegal_cache = 0;
 
        initial illegal_valid = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
 
                begin
                        illegal_cache <= 0;
                        illegal_cache <= 0;
                else if ((o_wb_cyc)&&(i_wb_err))
                        illegal_valid <= 0;
 
                end else if ((o_wb_cyc)&&(i_wb_err))
 
                begin
                        illegal_cache <= lastpc[(AW-1):PW];
                        illegal_cache <= lastpc[(AW-1):PW];
 
                        illegal_valid <= 1'b1;
 
                end
 
 
        initial o_illegal = 1'b0;
        initial o_illegal = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stall_n)
                if ((i_rst)||(i_clear_cache))
                        o_illegal <= (illegal_cache == lastpc[(AW-1):PW]);
                        o_illegal <= 1'b0;
 
                else
 
                        o_illegal <= (illegal_valid)
 
                                &&(tagval == i_pc[(AW-1):CW])
 
                                &&(illegal_cache == i_pc[(AW-1):PW]);
 
 
endmodule
endmodule
 
 
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