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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: pfcache2.v
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// Filename: pfcache.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: Keeping our CPU fed with instructions, at one per clock and
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// Purpose: Keeping our CPU fed with instructions, at one per clock and
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// with no stalls. An unusual feature of this cache is the
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// with no stalls. An unusual feature of this cache is the
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reg [((1<<(CW-PW))-1):0] vmask;
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reg [((1<<(CW-PW))-1):0] vmask;
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reg [(AW-1):0] lastpc;
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reg [(AW-1):0] lastpc;
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reg [(CW-1):0] rdaddr;
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reg [(CW-1):0] rdaddr;
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reg [(AW-1):CW] tagval;
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reg [(AW-1):CW] tagval;
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reg [(AW-1):PW] lasttag, illegal_cache;
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wire [(AW-1):PW] lasttag;
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reg [(AW-1):PW] illegal_cache;
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initial o_i = 32'h76_00_00_00; // A NOOP instruction
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initial o_i = 32'h76_00_00_00; // A NOOP instruction
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initial o_pc = 0;
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initial o_pc = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~r_v)
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if (~r_v)
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o_pc <= i_pc;
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o_pc <= i_pc;
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end
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end
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initial tagval = 0;
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initial tagval = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stall_n)
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if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})
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&&(i_wb_ack)&&(~i_wb_err))
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// Our tag value changes any time we finish reading a
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// new cache line
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tagval <= o_wb_addr[(AW-1):CW];
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else if ((i_stall_n)&&(~o_wb_cyc))
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// Otherwise, as long as we're not reading new stuff,
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// the tag line changes any time the pipeline steps
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// forwards. Our purpose here is primarily just to
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// catch sudden changes. The result is that walking
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// from one cache line to the next will cost a clock.
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tagval <= tags[i_pc[(CW-1):PW]];
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tagval <= tags[i_pc[(CW-1):PW]];
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// i_pc will only increment when everything else isn't stalled, thus
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// i_pc will only increment when everything else isn't stalled, thus
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// we can set it without worrying about that. Doing this enables
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// we can set it without worrying about that. Doing this enables
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// us to work in spite of stalls. For example, if the next address
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// us to work in spite of stalls. For example, if the next address
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initial lastpc = 0;
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initial lastpc = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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lastpc <= i_pc;
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lastpc <= i_pc;
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initial lasttag = 0;
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assign lasttag = lastpc[(AW-1):PW];
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always @(posedge i_clk)
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// initial lasttag = 0;
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lasttag <= i_pc[(AW-1):PW];
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// always @(posedge i_clk)
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// if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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// lasttag <= i_pc[(AW-1):PW];
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wire r_v_from_pc, r_v_from_last;
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wire r_v_from_pc, r_v_from_last;
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assign r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
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assign r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
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&&(tagval == i_pc[(AW-1):CW])
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&&(tagval == i_pc[(AW-1):CW])
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&&(vmask[i_pc[(CW-1):PW]]));
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&&(vmask[i_pc[(CW-1):PW]]));
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assign r_v_from_last = ((lastpc[(AW-1):PW] == lasttag)
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assign r_v_from_last = (
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&&(tagval == lastpc[(AW-1):CW])
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//(lastpc[(AW-1):PW] == lasttag)&&
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(tagval == lastpc[(AW-1):CW])
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&&(vmask[lastpc[(CW-1):PW]]));
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&&(vmask[lastpc[(CW-1):PW]]));
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reg [1:0] delay;
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reg [1:0] delay;
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initial delay = 2'h3;
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initial delay = 2'h3;
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else
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else
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o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
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o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
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end
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end
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if (i_wb_ack)
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if (i_wb_ack)
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rdaddr <= rdaddr + 1;
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if ((rdaddr[(PW-1):0] == {(PW){1'b1}})||(i_wb_err))
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begin
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begin
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o_wb_cyc <= 1'b0;
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rdaddr <= rdaddr + 1;
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if (rdaddr[(PW-1):0] == {(PW){1'b1}})
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tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
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tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
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end
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end
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if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
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o_wb_cyc <= 1'b0;
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// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
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// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
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// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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end else if ((~r_v)&&(delay==0)
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end else if ((~r_v)&&(delay==0)
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&&((tagval != lastpc[(AW-1):CW])
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&&((tagval != lastpc[(AW-1):CW])
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