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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 201 and 209

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// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
// Copyright (C) 2015,2017,2019 Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
 
`default_nettype        none
 
//
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
                        o_i, o_pc, o_v,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
                        o_illegal);
                        o_illegal);
        parameter       RESET_ADDRESS=32'h0010_0000,
        parameter       RESET_ADDRESS=32'h0010_0000,
                        LGCACHELEN = 6, ADDRESS_WIDTH=24,
                        LGCACHELEN = 6, ADDRESS_WIDTH=24,
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
        input                           i_clk, i_rst, i_new_pc,
        input   wire                    i_clk, i_rst, i_new_pc,
                                        i_clear_cache, i_stall_n;
                                        i_clear_cache, i_stall_n;
        input           [(AW-1):0]       i_pc;
        input   wire    [(AW-1):0]       i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(AW-1):0]       o_pc;
        output  reg     [(AW-1):0]       o_pc;
        output  wire                    o_v;
        output  wire                    o_v;
        //
        //
        output  reg             o_wb_cyc, o_wb_stb;
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  wire            o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        //
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input   wire            i_wb_ack, i_wb_stall, i_wb_err;
        input           [(BUSW-1):0]     i_wb_data;
        input   wire    [(BUSW-1):0]     i_wb_data;
        //
        //
        // Is the (data) memory unit also requesting access to the bus?
        // Is the (data) memory unit also requesting access to the bus?
        input                           i_wb_request;
        input   wire                    i_wb_request;
        output  wire                    o_illegal;
        output  wire                    o_illegal;
 
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        // to zero just to set it to something.
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                                //              {(LGCACHELEN-1){1'b0}}})
                                //              {(LGCACHELEN-1){1'b0}}})
                                // (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
                                // (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
                                +(3<<(LGCACHELEN-2)))
                                +(3<<(LGCACHELEN-2)))
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
 
 
        initial r_cache_base = RESET_ADDRESS;
        initial r_cache_base = RESET_ADDRESS[(AW+1):2];
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
                if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
                begin
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_cyc <= 1'b0;
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                if ((o_wb_cyc)&&(i_wb_err))
                if ((o_wb_cyc)&&(i_wb_err))
                        ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
                        ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
 
 
        assign  o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
        assign  o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
 
 
 
 
endmodule
endmodule
 
 
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