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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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// Copyright (C) 2015,2017,2019 Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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//
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module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
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module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
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o_i, o_pc, o_v,
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o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
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o_illegal);
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o_illegal);
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parameter RESET_ADDRESS=32'h0010_0000,
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parameter RESET_ADDRESS=32'h0010_0000,
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LGCACHELEN = 6, ADDRESS_WIDTH=24,
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LGCACHELEN = 6, ADDRESS_WIDTH=24,
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CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
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CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
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input i_clk, i_rst, i_new_pc,
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input wire i_clk, i_rst, i_new_pc,
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i_clear_cache, i_stall_n;
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i_clear_cache, i_stall_n;
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input [(AW-1):0] i_pc;
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input wire [(AW-1):0] i_pc;
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output reg [(BUSW-1):0] o_i;
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output reg [(BUSW-1):0] o_i;
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output reg [(AW-1):0] o_pc;
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output reg [(AW-1):0] o_pc;
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output wire o_v;
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output wire o_v;
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//
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//
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output reg o_wb_cyc, o_wb_stb;
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output wire o_wb_we;
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output reg [(AW-1):0] o_wb_addr;
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output reg [(AW-1):0] o_wb_addr;
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output wire [(BUSW-1):0] o_wb_data;
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output wire [(BUSW-1):0] o_wb_data;
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//
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//
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input i_wb_ack, i_wb_stall, i_wb_err;
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input wire i_wb_ack, i_wb_stall, i_wb_err;
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input [(BUSW-1):0] i_wb_data;
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input wire [(BUSW-1):0] i_wb_data;
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//
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//
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// Is the (data) memory unit also requesting access to the bus?
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// Is the (data) memory unit also requesting access to the bus?
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input i_wb_request;
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input wire i_wb_request;
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output wire o_illegal;
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output wire o_illegal;
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// Fixed bus outputs: we read from the bus only, never write.
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// Fixed bus outputs: we read from the bus only, never write.
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// Thus the output data is ... irrelevant and don't care. We set it
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// Thus the output data is ... irrelevant and don't care. We set it
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// to zero just to set it to something.
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// to zero just to set it to something.
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// {(LGCACHELEN-1){1'b0}}})
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// {(LGCACHELEN-1){1'b0}}})
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// (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
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// (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
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+(3<<(LGCACHELEN-2)))
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+(3<<(LGCACHELEN-2)))
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&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
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&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
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initial r_cache_base = RESET_ADDRESS;
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initial r_cache_base = RESET_ADDRESS[(AW+1):2];
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
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if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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if ((o_wb_cyc)&&(i_wb_err))
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if ((o_wb_cyc)&&(i_wb_err))
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ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
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ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
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assign o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
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assign o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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