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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 3 and 11

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Rev 3 Rev 11
Line 162... Line 162...
                        end
                        end
                end
                end
        end
        end
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&(
                if (i_rst) // Required, so we can reload memoy and then reset
 
                        r_nvalid <= 0;
 
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_nvalid <= 0;
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                else if ((o_wb_cyc)&&(i_wb_ack))
                else if ((o_wb_cyc)&&(i_wb_ack))

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