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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 2 and 3

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////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    regset.v
// Filename:    pipefetch.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
 
//              with no stalls, can be quite a chore.  Worse, the Wishbone
 
//              takes a couple of cycles just to read one instruction from
 
//              the bus.  However, if we use pipeline accesses to the Wishbone
 
//              bus, then we can read more and faster.  Further, if we cache
 
//              these results so that we have them before we need them, then
 
//              we have a chance of keeping our CPU from stalling.  Those are
 
//              the purposes of this instruction fetch module: 1) Pipeline
 
//              wishbone accesses, and 2) an instruction cache.
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
module  pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,
module  pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,
                        o_i, o_pc, o_v,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data);
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
        parameter       LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN), BUSW=32;
        parameter       RESET_ADDRESS=32'h0010_0000,
 
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
 
                        BUSW=32;
        input                           i_clk, i_rst, i_new_pc, i_stall_n;
        input                           i_clk, i_rst, i_new_pc, i_stall_n;
        input           [(BUSW-1):0]     i_pc;
        input           [(BUSW-1):0]     i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_pc;
        output  reg     [(BUSW-1):0]     o_pc;
        output  wire                    o_v;
        output  wire                    o_v;
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        output  reg     [(BUSW-1):0]     o_wb_addr;
        output  reg     [(BUSW-1):0]     o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        //
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [(BUSW-1):0]     i_wb_data;
        input           [(BUSW-1):0]     i_wb_data;
 
        //
 
        // Is the (data) memory unit also requesting access to the bus?
 
        input                           i_wb_request;
 
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
        assign  o_wb_data = 0;
 
 
        reg     [(BUSW-1):0]             r_cache_base, r_cache_offset;
        reg     [(BUSW-1):0]             r_cache_base;
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
 
 
        wire    [(LGCACHELEN-1):0]       c_cache_offset;
        reg     [(LGCACHELEN-1):0]       r_cache_offset;
        assign  c_cache_offset =  r_cache_offset[(LGCACHELEN-1):0];
 
 
 
        reg                     r_addr_set;
        reg                     r_addr_set;
        reg     [(BUSW-1):0]     r_addr;
        reg     [(BUSW-1):0]     r_addr;
 
 
        wire    [(BUSW-1):0]     bus_nvalid;
        wire    [(BUSW-1):0]     bus_nvalid;
        assign  bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
        assign  bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
 
 
 
        // What are some of the conditions for which we need to restart the
 
        // cache?
 
        wire    w_pc_out_of_bounds;
 
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
 
                                        ||(i_pc < r_cache_base)
 
                                        ||(i_pc >= r_cache_base + CACHELEN)));
 
        wire    w_ran_off_end_of_cache;
 
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
 
                                        ||(r_addr >= r_cache_base + CACHELEN)));
 
        wire    w_running_out_of_cache;
 
        assign  w_running_out_of_cache = (r_addr_set)
 
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
 
                                                + (1<<(LGCACHELEN-1)));
        initial r_nvalid = 0;
        initial r_nvalid = 0;
        initial r_cache_base = 0;
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if (i_rst)
                if (i_rst)
                        o_wb_cyc <= 1'b0;
 
                else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
 
                                &&(i_pc > r_cache_base)
 
                                &&(i_pc < r_cache_base + bus_nvalid))
 
                begin
                begin
 
                        o_wb_cyc <= 1'b0;
 
                        // r_cache_base <= RESET_ADDRESS;
 
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
 
                //              &&(i_pc >= r_cache_base)
 
                //              &&(i_pc < r_cache_base + bus_nvalid))
 
                // begin
                        // The new instruction is in our cache, do nothing
                        // The new instruction is in our cache, do nothing
                        // with the bus here.
                        // with the bus here.
                end else if ((o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
                end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
                                &&((i_pc < r_cache_base)
 
                                        ||(i_pc >= r_cache_base + CACHELEN)))
 
                begin
                begin
                        // We need to abandon our bus action to start over in
                        // We need to abandon our bus action to start over in
                        // a new region, setting up a new cache.  This may
                        // a new region, setting up a new cache.  This may
                        // happen mid cycle while waiting for a result.  By
                        // happen mid cycle while waiting for a result.  By
                        // dropping o_wb_cyc, we state that we are no longer
                        // dropping o_wb_cyc, we state that we are no longer
                        // interested in that result--whatever it might be.
                        // interested in that result--whatever it might be.
                        o_wb_cyc <= 1'b0;
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                        o_wb_stb <= 1'b0;
 
                end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
 
                begin
 
                        // Restart a bus cycle that was interrupted when the
 
                        // data section wanted access to our bus.
 
                        o_wb_cyc <= 1'b1;
 
                        o_wb_stb <= 1'b1;
 
                        // o_wb_addr <= r_cache_base + bus_nvalid;
                end else if ((~o_wb_cyc)&&(
                end else if ((~o_wb_cyc)&&(
                                ((i_new_pc)&&((r_nvalid == 0)
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                                        ||(i_pc < r_cache_base)
 
                                        ||(i_pc >= r_cache_base + CACHELEN)))
 
                                ||((r_addr_set)&&((r_addr < r_cache_base)
 
                                        ||(r_addr >= r_cache_base + CACHELEN)))
 
                                        ))
 
                begin
                begin
                        // Start a bus transaction
                        // Start a bus transaction
                        o_wb_cyc <= 1'b1;
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        o_wb_stb <= 1'b1;
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        // o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        r_acks_waiting <= 0;
                        // r_nvalid <= 0;
                        r_nvalid <= 0;
                        // r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                        // r_cache_offset <= 0;
                        r_cache_offset <= 0;
                end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                end else if ((~o_wb_cyc)&&(r_addr_set)
 
                                        &&(r_addr >= r_cache_base
 
                                                        + (1<<(LGCACHELEN-2))
 
                                                        + (1<<(LGCACHELEN-1))))
 
                begin
                begin
                        // If we're using the last quarter of the cache, then
                        // If we're using the last quarter of the cache, then
                        // let's start a bus transaction to extend the cache.
                        // let's start a bus transaction to extend the cache.
                        o_wb_cyc <= 1'b1;
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        o_wb_stb <= 1'b1;
                        o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
                        // o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
                        r_acks_waiting <= 0;
                        // r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                        // r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
                        // r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
 
                end else if (o_wb_cyc)
                end else if (o_wb_cyc)
                begin
                begin
                        // This handles everything ... but the case where
                        // This handles everything ... but the case where
                        // while reading we need to extend our cache.
                        // while reading we need to extend our cache.
                        if ((o_wb_stb)&&(~i_wb_stall))
                        if ((o_wb_stb)&&(~i_wb_stall))
                        begin
                        begin
                                o_wb_addr <= o_wb_addr + 1;
                                // o_wb_addr <= o_wb_addr + 1;
                                if (o_wb_addr - r_cache_base >= CACHELEN-1)
                                if ((o_wb_addr - r_cache_base >= CACHELEN-1)
 
                                        ||(i_wb_request))
                                        o_wb_stb <= 1'b0;
                                        o_wb_stb <= 1'b0;
                        end
                        end
 
 
                        if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
 
                                r_acks_waiting <= r_acks_waiting
 
                                                + ((i_wb_ack)? 0:1);
 
                        else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
 
                                r_acks_waiting <= r_acks_waiting - 1;
 
 
 
                        if (i_wb_ack)
                        if (i_wb_ack)
                        begin
                        begin
                                cache[r_nvalid[(LGCACHELEN-1):0]+c_cache_offset] <= i_wb_data;
                                // r_nvalid <= r_nvalid + 1;
                                r_nvalid <= r_nvalid + 1;
 
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
                                        o_wb_cyc <= 1'b0;
                                        o_wb_cyc <= 1'b0;
                        end
                        end
                end
                end
        end
        end
 
 
 
        always @(posedge i_clk)
 
                if ((~o_wb_cyc)&&(
 
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
 
                        r_nvalid <= 0;
 
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
 
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
 
                else if ((o_wb_cyc)&&(i_wb_ack))
 
                        r_nvalid <= r_nvalid+1;
 
 
 
        always @(posedge i_clk)
 
                if ((~o_wb_cyc)&&(
 
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
 
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
 
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
 
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
 
 
 
        always @(posedge i_clk)
 
                if ((~o_wb_cyc)&&(
 
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
 
                        r_cache_offset <= 0;
 
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
 
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
 
 
 
        always @(posedge i_clk)
 
                if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
 
                                        ||(w_ran_off_end_of_cache)))
 
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
 
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
 
                        o_wb_addr <= o_wb_addr + 1;
 
 
 
        initial r_acks_waiting = 0;
 
        always @(posedge i_clk)
 
                if (~o_wb_cyc)
 
                        r_acks_waiting <= 0;
 
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
 
                        r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1);
 
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
 
                                r_acks_waiting <= r_acks_waiting - 1;
 
 
 
        always @(posedge i_clk)
 
                if ((o_wb_cyc)&&(i_wb_ack))
 
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
 
                                        <= i_wb_data;
 
 
        initial r_addr_set = 1'b0;
        initial r_addr_set = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_addr_set <= 1'b0;
                        r_addr_set <= 1'b0;
                else if (i_new_pc)
                else if (i_new_pc)
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                else if ((i_stall_n)&&(w_cv))
                else if ((i_stall_n)&&(w_cv))
                        r_addr <= r_addr + 1;
                        r_addr <= r_addr + 1;
 
 
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+c_cache_offset;
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stall_n)
                if (i_stall_n)
                        o_i <= cache[c_rdaddr];
                        o_i <= cache[c_rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stall_n)
                if (i_stall_n)

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