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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 18 and 36

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Line 12... Line 12...
//              these results so that we have them before we need them, then
//              these results so that we have them before we need them, then
//              we have a chance of keeping our CPU from stalling.  Those are
//              we have a chance of keeping our CPU from stalling.  Those are
//              the purposes of this instruction fetch module: 1) Pipeline
//              the purposes of this instruction fetch module: 1) Pipeline
//              wishbone accesses, and 2) an instruction cache.
//              wishbone accesses, and 2) an instruction cache.
//
//
 
//      20150919 -- Fixed a nasty race condition whereby the pipefetch routine
 
//              would produce either the same instruction twice, or skip
 
//              an instruction.  This condition was dependent on the CPU stall
 
//              condition, and would only take place if the pipeline wasn't 
 
//              completely full throughout the stall.
 
//
 
//              Interface support was also added for trapping on illegal
 
//              instructions (i.e., instruction fetches that cause bus errors),
 
//              however the internal interface has not caught up to supporting
 
//              these exceptions yet.
 
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
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////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
                        o_i, o_pc, o_v,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
 
                        o_illegal);
        parameter       RESET_ADDRESS=32'h0010_0000,
        parameter       RESET_ADDRESS=32'h0010_0000,
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
                        BUSW=32;
                        BUSW=32;
        input                           i_clk, i_rst, i_new_pc,
        input                           i_clk, i_rst, i_new_pc,
                                        i_clear_cache, i_stall_n;
                                        i_clear_cache, i_stall_n;
Line 54... Line 66...
        output  reg             o_wb_cyc, o_wb_stb;
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  wire            o_wb_we;
        output  reg     [(BUSW-1):0]     o_wb_addr;
        output  reg     [(BUSW-1):0]     o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        //
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [(BUSW-1):0]     i_wb_data;
        input           [(BUSW-1):0]     i_wb_data;
        //
        //
        // Is the (data) memory unit also requesting access to the bus?
        // Is the (data) memory unit also requesting access to the bus?
        input                           i_wb_request;
        input                           i_wb_request;
 
        output  wire                    o_illegal;
 
 
 
        assign  o_illegal = 1'b0;
 
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_we = 1'b0;
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                                        ||(r_addr >= r_cache_base + CACHELEN)));
                                        ||(r_addr >= r_cache_base + CACHELEN)));
        wire    w_running_out_of_cache;
        wire    w_running_out_of_cache;
        assign  w_running_out_of_cache = (r_addr_set)
        assign  w_running_out_of_cache = (r_addr_set)
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
                                                + (1<<(LGCACHELEN-1)));
                                                + (1<<(LGCACHELEN-1)));
        initial r_nvalid = 0;
 
        initial r_cache_base = RESET_ADDRESS;
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
                begin
                begin
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                        if (i_wb_ack)
                        if (i_wb_ack)
                        begin
                        begin
                                // r_nvalid <= r_nvalid + 1;
                                // r_nvalid <= r_nvalid + 1;
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
                                        o_wb_cyc <= 1'b0;
                                        o_wb_cyc <= 1'b0;
                        end
                        end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
 
                                o_wb_cyc <= 1'b0;
                end
                end
        end
        end
 
 
 
        initial r_nvalid = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
                        r_nvalid <= 0;
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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        initial r_acks_waiting = 0;
        initial r_acks_waiting = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (~o_wb_cyc)
                if (~o_wb_cyc)
                        r_acks_waiting <= 0;
                        r_acks_waiting <= 0;
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
                        r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1);
                        r_acks_waiting <= r_acks_waiting + 1;
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
                                r_acks_waiting <= r_acks_waiting - 1;
                                r_acks_waiting <= r_acks_waiting - 1;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
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        wire    w_cv;   // Cache valid, address is in the cache
        wire    w_cv;   // Cache valid, address is in the cache
        reg     r_cv;
        reg     r_cv;
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
                        &&(r_addr-r_cache_base < bus_nvalid));
                        &&(r_addr-r_cache_base < bus_nvalid));
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_cv <= (~i_new_pc)&&(w_cv);
                r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv)));
        assign  o_v = (r_cv)&&(~i_new_pc);
        assign  o_v = (r_cv)&&(~i_new_pc);
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_new_pc)
                if (i_new_pc)
                        r_addr <= i_pc;
                        r_addr <= i_pc;
                else if ((i_stall_n)&&(w_cv))
                else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
                        r_addr <= r_addr + 1;
                        r_addr <= r_addr + 1;
 
 
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stall_n)
                if ((~o_v)||((i_stall_n)&&(o_v)))
                        o_i <= cache[c_rdaddr];
                        o_i <= cache[c_rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_stall_n)
                if ((~o_v)||((i_stall_n)&&(o_v)))
                        o_pc <= r_addr;
                        o_pc <= r_addr;
 
 
endmodule
endmodule
 
 
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