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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 36 and 38

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Rev 36 Rev 38
Line 213... Line 213...
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_clear_cache)
                if (i_clear_cache)
                        o_wb_addr <= i_pc;
                        o_wb_addr <= i_pc;
                else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
 
                begin
 
                        if (i_wb_ack)
 
                                o_wb_addr <= r_cache_base + bus_nvalid+1;
 
                        else
 
                                o_wb_addr <= r_cache_base + bus_nvalid;
 
                end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                                        ||(w_ran_off_end_of_cache)))
                                        ||(w_ran_off_end_of_cache)))
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                        o_wb_addr <= o_wb_addr + 1;
                        o_wb_addr <= o_wb_addr + 1;
 
 
        initial r_acks_waiting = 0;
        initial r_acks_waiting = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (~o_wb_cyc)
                if (~o_wb_cyc)
                        r_acks_waiting <= 0;
                        r_acks_waiting <= 0;
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
                        r_acks_waiting <= r_acks_waiting + 1;
                        r_acks_waiting <= r_acks_waiting + 1;
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
                else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
                        r_acks_waiting <= r_acks_waiting - 1;
                        r_acks_waiting <= r_acks_waiting - 1;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]

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