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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 38 and 48

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Rev 38 Rev 48
Line 52... Line 52...
                        o_i, o_pc, o_v,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
                        o_illegal);
                        o_illegal);
        parameter       RESET_ADDRESS=32'h0010_0000,
        parameter       RESET_ADDRESS=32'h0010_0000,
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
                        LGCACHELEN = 6, ADDRESS_WIDTH=24,
                        BUSW=32;
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
        input                           i_clk, i_rst, i_new_pc,
        input                           i_clk, i_rst, i_new_pc,
                                        i_clear_cache, i_stall_n;
                                        i_clear_cache, i_stall_n;
        input           [(BUSW-1):0]     i_pc;
        input           [(AW-1):0]       i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_pc;
        output  reg     [(AW-1):0]       o_pc;
        output  wire                    o_v;
        output  wire                    o_v;
        //
        //
        output  reg             o_wb_cyc, o_wb_stb;
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  wire            o_wb_we;
        output  reg     [(BUSW-1):0]     o_wb_addr;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        //
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [(BUSW-1):0]     i_wb_data;
        input           [(BUSW-1):0]     i_wb_data;
        //
        //
Line 81... Line 81...
        // Thus the output data is ... irrelevant and don't care.  We set it
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
        assign  o_wb_data = 0;
 
 
        reg     [(BUSW-1):0]             r_cache_base;
        reg     [(AW-1):0]               r_cache_base;
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
 
 
        reg     [(LGCACHELEN-1):0]       r_cache_offset;
        reg     [(LGCACHELEN-1):0]       r_cache_offset;
 
 
        reg                     r_addr_set;
        reg                     r_addr_set;
        reg     [(BUSW-1):0]     r_addr;
        reg     [(AW-1):0]       r_addr;
 
 
        wire    [(BUSW-1):0]     bus_nvalid;
        wire    [(AW-1):0]       bus_nvalid;
        assign  bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
        assign  bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid };
 
 
        // What are some of the conditions for which we need to restart the
        // What are some of the conditions for which we need to restart the
        // cache?
        // cache?
        wire    w_pc_out_of_bounds;
        wire    w_pc_out_of_bounds;
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
                                        ||(i_pc < r_cache_base)
                                        ||(i_pc < r_cache_base)
                                        ||(i_pc >= r_cache_base + CACHELEN)));
                                        ||(i_pc >= r_cache_base + CACHELEN)
 
                                        ||(i_pc >= r_cache_base + bus_nvalid+5)));
        wire    w_ran_off_end_of_cache;
        wire    w_ran_off_end_of_cache;
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
                                        ||(r_addr >= r_cache_base + CACHELEN)));
                                        ||(r_addr >= r_cache_base + CACHELEN)
 
                                        ||(r_addr >= r_cache_base + bus_nvalid+5)));
        wire    w_running_out_of_cache;
        wire    w_running_out_of_cache;
        assign  w_running_out_of_cache = (r_addr_set)
        assign  w_running_out_of_cache = (r_addr_set)
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
                                                + (1<<(LGCACHELEN-1)));
                                                + (1<<(LGCACHELEN-1)))
 
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
 
 
        initial r_cache_base = RESET_ADDRESS;
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache))
                begin
                begin

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