Line 85... |
Line 85... |
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reg [(AW-1):0] r_cache_base;
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reg [(AW-1):0] r_cache_base;
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reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
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reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
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reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
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reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
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reg [(LGCACHELEN-1):0] r_cache_offset;
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wire [(LGCACHELEN-1):0] w_cache_offset;
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reg [1:0] r_cache_offset;
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reg r_addr_set;
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reg r_addr_set;
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reg [(AW-1):0] r_addr;
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reg [(AW-1):0] r_addr;
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wire [(AW-1):0] bus_nvalid;
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wire [(AW-1):0] bus_nvalid;
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Line 106... |
Line 107... |
assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
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assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
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||(r_addr >= r_cache_base + CACHELEN)
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||(r_addr >= r_cache_base + CACHELEN)
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||(r_addr >= r_cache_base + bus_nvalid+5)));
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||(r_addr >= r_cache_base + bus_nvalid+5)));
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wire w_running_out_of_cache;
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wire w_running_out_of_cache;
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assign w_running_out_of_cache = (r_addr_set)
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assign w_running_out_of_cache = (r_addr_set)
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&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
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&&(r_addr >= r_cache_base +
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+ (1<<(LGCACHELEN-1)))
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// {{(AW-LGCACHELEN-1),{1'b0}},2'b11,
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// {(LGCACHELEN-1){1'b0}}})
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// (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
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+(3<<(LGCACHELEN-2)))
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&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
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&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
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initial r_cache_base = RESET_ADDRESS;
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initial r_cache_base = RESET_ADDRESS;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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Line 149... |
Line 153... |
o_wb_cyc <= 1'b1;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_stb <= 1'b1;
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// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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// r_nvalid <= 0;
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// r_nvalid <= 0;
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// r_cache_base <= (i_new_pc) ? i_pc : r_addr;
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// r_cache_base <= (i_new_pc) ? i_pc : r_addr;
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// r_cache_offset <= 0;
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// w_cache_offset <= 0;
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end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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begin
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begin
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// If we're using the last quarter of the cache, then
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// If we're using the last quarter of the cache, then
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// let's start a bus transaction to extend the cache.
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// let's start a bus transaction to extend the cache.
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o_wb_cyc <= 1'b1;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_stb <= 1'b1;
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// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
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// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
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// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
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// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
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// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
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// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
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// r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
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// w_cache_offset <= w_cache_offset + (1<<(LGCACHELEN-2));
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end else if (o_wb_cyc)
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end else if (o_wb_cyc)
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begin
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begin
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// This handles everything ... but the case where
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// This handles everything ... but the case where
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// while reading we need to extend our cache.
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// while reading we need to extend our cache.
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if ((o_wb_stb)&&(~i_wb_stall))
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if ((o_wb_stb)&&(~i_wb_stall))
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Line 190... |
Line 194... |
r_nvalid <= 0;
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r_nvalid <= 0;
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else if ((~o_wb_cyc)&&(
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else if ((~o_wb_cyc)&&(
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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r_nvalid <= 0;
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r_nvalid <= 0;
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
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r_nvalid[LGCACHELEN:(LGCACHELEN-2)]
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<= r_nvalid[LGCACHELEN:(LGCACHELEN-2)] +3'b111;
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// i.e. - (1<<(LGCACHELEN-2));
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else if ((o_wb_cyc)&&(i_wb_ack))
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else if ((o_wb_cyc)&&(i_wb_ack))
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r_nvalid <= r_nvalid+1;
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r_nvalid <= r_nvalid + {{(LGCACHELEN){1'b0}},1'b1}; // +1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_clear_cache)
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if (i_clear_cache)
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r_cache_base <= i_pc;
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r_cache_base <= i_pc;
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else if ((~o_wb_cyc)&&(
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else if ((~o_wb_cyc)&&(
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(w_pc_out_of_bounds)
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(w_pc_out_of_bounds)
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||(w_ran_off_end_of_cache)))
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||(w_ran_off_end_of_cache)))
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r_cache_base <= (i_new_pc) ? i_pc : r_addr;
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r_cache_base <= (i_new_pc) ? i_pc : r_addr;
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
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r_cache_base[(AW-1):(LGCACHELEN-2)]
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<= r_cache_base[(AW-1):(LGCACHELEN-2)]
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+ {{(AW-LGCACHELEN+1){1'b0}},1'b1};
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// i.e. + (1<<(LGCACHELEN-2));
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_clear_cache)
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if (i_clear_cache)
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r_cache_offset <= 0;
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r_cache_offset <= 0;
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else if ((~o_wb_cyc)&&(
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else if ((~o_wb_cyc)&&(
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(w_pc_out_of_bounds)
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(w_pc_out_of_bounds)
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||(w_ran_off_end_of_cache)))
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||(w_ran_off_end_of_cache)))
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r_cache_offset <= 0;
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r_cache_offset <= 0;
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
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r_cache_offset[1:0] <= r_cache_offset[1:0] + 2'b01;
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assign w_cache_offset = { r_cache_offset, {(LGCACHELEN-2){1'b0}} };
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_clear_cache)
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if (i_clear_cache)
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o_wb_addr <= i_pc;
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o_wb_addr <= i_pc;
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else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
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else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
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Line 234... |
Line 244... |
initial r_acks_waiting = 0;
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initial r_acks_waiting = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_cyc)
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if (~o_wb_cyc)
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r_acks_waiting <= 0;
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r_acks_waiting <= 0;
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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r_acks_waiting <= r_acks_waiting + 1;
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r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
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else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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r_acks_waiting <= r_acks_waiting - 1;
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r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
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cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
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<= i_wb_data;
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<= i_wb_data;
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initial r_addr_set = 1'b0;
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initial r_addr_set = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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Line 263... |
Line 273... |
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_new_pc)
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if (i_new_pc)
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r_addr <= i_pc;
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r_addr <= i_pc;
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else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
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else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
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r_addr <= r_addr + 1;
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r_addr <= r_addr + {{(AW-1){1'b0}},1'b1};
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wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
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wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
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assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
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assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
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assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
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assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+w_cache_offset;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~o_v)||((i_stall_n)&&(o_v)))
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if ((~o_v)||((i_stall_n)&&(o_v)))
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o_i <= cache[c_rdaddr];
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o_i <= cache[c_rdaddr];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~o_v)||((i_stall_n)&&(o_v)))
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if ((~o_v)||((i_stall_n)&&(o_v)))
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