| Line 85... |
Line 85... |
|
|
reg [(AW-1):0] r_cache_base;
|
reg [(AW-1):0] r_cache_base;
|
reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
|
reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
|
reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
|
reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
|
|
|
reg [(LGCACHELEN-1):0] r_cache_offset;
|
wire [(LGCACHELEN-1):0] w_cache_offset;
|
|
reg [1:0] r_cache_offset;
|
|
|
reg r_addr_set;
|
reg r_addr_set;
|
reg [(AW-1):0] r_addr;
|
reg [(AW-1):0] r_addr;
|
|
|
wire [(AW-1):0] bus_nvalid;
|
wire [(AW-1):0] bus_nvalid;
|
| Line 106... |
Line 107... |
assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
|
assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
|
||(r_addr >= r_cache_base + CACHELEN)
|
||(r_addr >= r_cache_base + CACHELEN)
|
||(r_addr >= r_cache_base + bus_nvalid+5)));
|
||(r_addr >= r_cache_base + bus_nvalid+5)));
|
wire w_running_out_of_cache;
|
wire w_running_out_of_cache;
|
assign w_running_out_of_cache = (r_addr_set)
|
assign w_running_out_of_cache = (r_addr_set)
|
&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
|
&&(r_addr >= r_cache_base +
|
+ (1<<(LGCACHELEN-1)))
|
// {{(AW-LGCACHELEN-1),{1'b0}},2'b11,
|
|
// {(LGCACHELEN-1){1'b0}}})
|
|
// (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
|
|
+(3<<(LGCACHELEN-2)))
|
&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
|
&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
|
|
|
initial r_cache_base = RESET_ADDRESS;
|
initial r_cache_base = RESET_ADDRESS;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
| Line 149... |
Line 153... |
o_wb_cyc <= 1'b1;
|
o_wb_cyc <= 1'b1;
|
o_wb_stb <= 1'b1;
|
o_wb_stb <= 1'b1;
|
// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
|
// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
|
// r_nvalid <= 0;
|
// r_nvalid <= 0;
|
// r_cache_base <= (i_new_pc) ? i_pc : r_addr;
|
// r_cache_base <= (i_new_pc) ? i_pc : r_addr;
|
// r_cache_offset <= 0;
|
// w_cache_offset <= 0;
|
end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
begin
|
begin
|
// If we're using the last quarter of the cache, then
|
// If we're using the last quarter of the cache, then
|
// let's start a bus transaction to extend the cache.
|
// let's start a bus transaction to extend the cache.
|
o_wb_cyc <= 1'b1;
|
o_wb_cyc <= 1'b1;
|
o_wb_stb <= 1'b1;
|
o_wb_stb <= 1'b1;
|
// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
|
// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
|
// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
|
// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
|
// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
|
// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
|
// r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
|
// w_cache_offset <= w_cache_offset + (1<<(LGCACHELEN-2));
|
end else if (o_wb_cyc)
|
end else if (o_wb_cyc)
|
begin
|
begin
|
// This handles everything ... but the case where
|
// This handles everything ... but the case where
|
// while reading we need to extend our cache.
|
// while reading we need to extend our cache.
|
if ((o_wb_stb)&&(~i_wb_stall))
|
if ((o_wb_stb)&&(~i_wb_stall))
|
| Line 190... |
Line 194... |
r_nvalid <= 0;
|
r_nvalid <= 0;
|
else if ((~o_wb_cyc)&&(
|
else if ((~o_wb_cyc)&&(
|
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
|
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
|
r_nvalid <= 0;
|
r_nvalid <= 0;
|
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
|
r_nvalid[LGCACHELEN:(LGCACHELEN-2)]
|
|
<= r_nvalid[LGCACHELEN:(LGCACHELEN-2)] +3'b111;
|
|
// i.e. - (1<<(LGCACHELEN-2));
|
else if ((o_wb_cyc)&&(i_wb_ack))
|
else if ((o_wb_cyc)&&(i_wb_ack))
|
r_nvalid <= r_nvalid+1;
|
r_nvalid <= r_nvalid + {{(LGCACHELEN){1'b0}},1'b1}; // +1;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_clear_cache)
|
if (i_clear_cache)
|
r_cache_base <= i_pc;
|
r_cache_base <= i_pc;
|
else if ((~o_wb_cyc)&&(
|
else if ((~o_wb_cyc)&&(
|
(w_pc_out_of_bounds)
|
(w_pc_out_of_bounds)
|
||(w_ran_off_end_of_cache)))
|
||(w_ran_off_end_of_cache)))
|
r_cache_base <= (i_new_pc) ? i_pc : r_addr;
|
r_cache_base <= (i_new_pc) ? i_pc : r_addr;
|
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
|
r_cache_base[(AW-1):(LGCACHELEN-2)]
|
|
<= r_cache_base[(AW-1):(LGCACHELEN-2)]
|
|
+ {{(AW-LGCACHELEN+1){1'b0}},1'b1};
|
|
// i.e. + (1<<(LGCACHELEN-2));
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_clear_cache)
|
if (i_clear_cache)
|
r_cache_offset <= 0;
|
r_cache_offset <= 0;
|
else if ((~o_wb_cyc)&&(
|
else if ((~o_wb_cyc)&&(
|
(w_pc_out_of_bounds)
|
(w_pc_out_of_bounds)
|
||(w_ran_off_end_of_cache)))
|
||(w_ran_off_end_of_cache)))
|
r_cache_offset <= 0;
|
r_cache_offset <= 0;
|
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
|
r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
|
r_cache_offset[1:0] <= r_cache_offset[1:0] + 2'b01;
|
|
assign w_cache_offset = { r_cache_offset, {(LGCACHELEN-2){1'b0}} };
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_clear_cache)
|
if (i_clear_cache)
|
o_wb_addr <= i_pc;
|
o_wb_addr <= i_pc;
|
else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
|
else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
|
| Line 234... |
Line 244... |
initial r_acks_waiting = 0;
|
initial r_acks_waiting = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~o_wb_cyc)
|
if (~o_wb_cyc)
|
r_acks_waiting <= 0;
|
r_acks_waiting <= 0;
|
else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
|
else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
|
r_acks_waiting <= r_acks_waiting + 1;
|
r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
|
else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
|
else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
|
r_acks_waiting <= r_acks_waiting - 1;
|
r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((o_wb_cyc)&&(i_wb_ack))
|
if ((o_wb_cyc)&&(i_wb_ack))
|
cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
|
cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
|
<= i_wb_data;
|
<= i_wb_data;
|
|
|
initial r_addr_set = 1'b0;
|
initial r_addr_set = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_cache))
|
if ((i_rst)||(i_clear_cache))
|
| Line 263... |
Line 273... |
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_new_pc)
|
if (i_new_pc)
|
r_addr <= i_pc;
|
r_addr <= i_pc;
|
else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
|
else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
|
r_addr <= r_addr + 1;
|
r_addr <= r_addr + {{(AW-1){1'b0}},1'b1};
|
|
|
wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
|
wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
|
assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
|
assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
|
assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
|
assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+w_cache_offset;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((~o_v)||((i_stall_n)&&(o_v)))
|
if ((~o_v)||((i_stall_n)&&(o_v)))
|
o_i <= cache[c_rdaddr];
|
o_i <= cache[c_rdaddr];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((~o_v)||((i_stall_n)&&(o_v)))
|
if ((~o_v)||((i_stall_n)&&(o_v)))
|
