OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 56 and 63

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 56 Rev 63
Line 73... Line 73...
        //
        //
        // Is the (data) memory unit also requesting access to the bus?
        // Is the (data) memory unit also requesting access to the bus?
        input                           i_wb_request;
        input                           i_wb_request;
        output  wire                    o_illegal;
        output  wire                    o_illegal;
 
 
        assign  o_illegal = 1'b0;
 
 
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
        assign  o_wb_data = 0;
Line 117... Line 115...
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
 
 
        initial r_cache_base = RESET_ADDRESS;
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
                begin
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                        o_wb_stb <= 1'b0;
                        // r_cache_base <= RESET_ADDRESS;
                        // r_cache_base <= RESET_ADDRESS;
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
Line 186... Line 184...
                        end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
                        end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
                                o_wb_cyc <= 1'b0;
                                o_wb_cyc <= 1'b0;
                end
                end
        end
        end
 
 
 
 
        initial r_nvalid = 0;
        initial r_nvalid = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
                        r_nvalid <= 0;
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(
                else if ((~o_wb_cyc)&&(
Line 236... Line 235...
                        else
                        else
                                o_wb_addr <= r_cache_base + bus_nvalid;
                                o_wb_addr <= r_cache_base + bus_nvalid;
                end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                                        ||(w_ran_off_end_of_cache)))
                                        ||(w_ran_off_end_of_cache)))
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                else if ((o_wb_stb)&&(~i_wb_stall))     // && o_wb_cyc
                        o_wb_addr <= o_wb_addr + 1;
                        o_wb_addr <= o_wb_addr + 1;
 
 
        initial r_acks_waiting = 0;
        initial r_acks_waiting = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (~o_wb_cyc)
                if (~o_wb_cyc)
                        r_acks_waiting <= 0;
                        r_acks_waiting <= 0;
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
                // o_wb_cyc *must* be true for all following
 
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc)
                        r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
                        r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
                else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) //&&(o_wb_cyc)
                        r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
                        r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
                        cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
Line 285... Line 285...
                        o_i <= cache[c_rdaddr];
                        o_i <= cache[c_rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((~o_v)||((i_stall_n)&&(o_v)))
                if ((~o_v)||((i_stall_n)&&(o_v)))
                        o_pc <= r_addr;
                        o_pc <= r_addr;
 
 
 
        reg     [(AW-1):0]       ill_address;
 
        initial ill_address = 0;
 
        always @(posedge i_clk)
 
                if ((o_wb_cyc)&&(i_wb_err))
 
                        ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
 
 
 
        assign  o_illegal = (o_pc == ill_address);
 
 
 
 
endmodule
endmodule
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.