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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipemem.v] - Diff between revs 194 and 201

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///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    pipemem.v
// Filename:    pipemem.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
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//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
 
//
//
//
module  pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
module  pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
                i_op, i_addr, i_data, i_oreg,
                i_op, i_addr, i_data, i_oreg,
                        o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
                        o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                        o_wb_stb_gbl, o_wb_stb_lcl,
                        o_wb_stb_gbl, o_wb_stb_lcl,
                        o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
        parameter       ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
        parameter       ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0;
 
        localparam      AW=ADDRESS_WIDTH;
        input                   i_clk, i_rst;
        input                   i_clk, i_rst;
        input                   i_pipe_stb, i_lock;
        input                   i_pipe_stb, i_lock;
        // CPU interface
        // CPU interface
        input                   i_op;
        input   [2:0]            i_op;
        input           [31:0]   i_addr;
        input           [31:0]   i_addr;
        input           [31:0]   i_data;
        input           [31:0]   i_data;
        input           [4:0]    i_oreg;
        input           [4:0]    i_oreg;
        // CPU outputs
        // CPU outputs
        output  wire            o_busy;
        output  wire            o_busy;
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        output  reg             o_wb_stb_gbl;
        output  reg             o_wb_stb_gbl;
        output  wire            o_wb_cyc_lcl;
        output  wire            o_wb_cyc_lcl;
        output  reg             o_wb_stb_lcl, o_wb_we;
        output  reg             o_wb_stb_lcl, o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [31:0]   o_wb_data;
        output  reg     [31:0]   o_wb_data;
 
        output  reg     [3:0]    o_wb_sel;
        // Wishbone inputs
        // Wishbone inputs
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 
        reg     cyc;
        reg     cyc;
        reg                     r_wb_cyc_gbl, r_wb_cyc_lcl;
        reg                     r_wb_cyc_gbl, r_wb_cyc_lcl;
        reg     [3:0]            rdaddr, wraddr;
        reg     [3:0]            rdaddr, wraddr;
        wire    [3:0]            nxt_rdaddr;
        wire    [3:0]            nxt_rdaddr;
        reg     [(5-1):0]        fifo_oreg [0:15];
        reg     [(4+5-1):0]      fifo_oreg [0:15];
        initial rdaddr = 0;
        initial rdaddr = 0;
        initial wraddr = 0;
        initial wraddr = 0;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                fifo_oreg[wraddr] <= i_oreg;
                fifo_oreg[wraddr] <= { i_oreg, i_op[2:1], i_addr[1:0] };
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_wb_err))
                if ((i_rst)||(i_wb_err))
                        wraddr <= 0;
                        wraddr <= 0;
                else if (i_pipe_stb)
                else if (i_pipe_stb)
                        wraddr <= wraddr + 4'h1;
                        wraddr <= wraddr + 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_wb_err))
                if ((i_rst)||(i_wb_err))
                        rdaddr <= 0;
                        rdaddr <= 0;
                else if ((i_wb_ack)&&(cyc))
                else if ((i_wb_ack)&&(cyc))
                        rdaddr <= rdaddr + 4'h1;
                        rdaddr <= rdaddr + 1'b1;
        assign  nxt_rdaddr = rdaddr + 4'h1;
        assign  nxt_rdaddr = rdaddr + 1'b1;
 
 
        wire    gbl_stb, lcl_stb;
        wire    gbl_stb, lcl_stb;
        assign  lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
        assign  lcl_stb = (i_addr[31:24]==8'hff);
        assign  gbl_stb = (~lcl_stb);
        assign  gbl_stb = (~lcl_stb);
                        //= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
                        //= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
 
        initial cyc = 0;
        initial cyc = 0;
        initial r_wb_cyc_lcl = 0;
        initial r_wb_cyc_lcl = 0;
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                        // o_wb_addr <= i_addr[(AW-1):0];
                        // o_wb_addr <= i_addr[(AW-1):0];
                        // o_wb_data <= i_data;
                        // o_wb_data <= i_data;
                        // o_wb_we <= i_op
                        // o_wb_we <= i_op
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall))
                if ((!cyc)||(!i_wb_stall))
                begin
 
                        o_wb_addr <= i_addr[(AW-1):0];
 
                        o_wb_data <= i_data;
 
                end else if ((~cyc)&&(i_pipe_stb))
 
                begin
                begin
                        o_wb_addr <= i_addr[(AW-1):0];
                        o_wb_addr <= i_addr[(AW+1):2];
                        o_wb_data <= i_data;
                        if (!i_op[0]) // Always select everything on reads
 
                                o_wb_sel <= 4'b1111;    // Op is even
 
                        else casez({ i_op[2:1], i_addr[1:0] })
 
                                4'b100?: o_wb_sel <= 4'b1100;   // Op = 5
 
                                4'b101?: o_wb_sel <= 4'b0011;   // Op = 5
 
                                4'b1100: o_wb_sel <= 4'b1000;   // Op = 5
 
                                4'b1101: o_wb_sel <= 4'b0100;   // Op = 7
 
                                4'b1110: o_wb_sel <= 4'b0010;   // Op = 7
 
                                4'b1111: o_wb_sel <= 4'b0001;   // Op = 7
 
                                default: o_wb_sel <= 4'b1111;   // Op = 7
 
                        endcase
 
 
 
                        casez({ i_op[2:1], i_addr[1:0] })
 
                        4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };
 
                        4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };
 
                        4'b1100: o_wb_data <= {         i_data[7:0], 24'h00 };
 
                        4'b1101: o_wb_data <= {  8'h00, i_data[7:0], 16'h00 };
 
                        4'b1110: o_wb_data <= { 16'h00, i_data[7:0],  8'h00 };
 
                        4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };
 
                        default: o_wb_data <= i_data;
 
                        endcase
 
 
                end
                end
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_pipe_stb)&&(~cyc))
                if ((i_pipe_stb)&&(~cyc))
                        o_wb_we   <= i_op;
                        o_wb_we   <= i_op[0];
 
 
        initial o_valid = 1'b0;
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
                o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
        initial o_err = 1'b0;
        initial o_err = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_err <= (cyc)&&(i_wb_err);
                o_err <= (cyc)&&(i_wb_err);
        assign  o_busy = cyc;
        assign  o_busy = cyc;
 
 
 
        wire    [8:0]    w_wreg;
 
        assign  w_wreg = fifo_oreg[rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wreg <= fifo_oreg[rdaddr];
                o_wreg <= w_wreg[8:4];
        always @(posedge i_clk)
        always @(posedge i_clk)
                // if (i_wb_ack) isn't necessary, since o_valid won't be true
                casez(w_wreg[3:0])
                // then either.
                4'b1100: o_result = { 24'h00, i_wb_data[31:24] };
                o_result <= i_wb_data;
                4'b1101: o_result = { 24'h00, i_wb_data[23:16] };
 
                4'b1110: o_result = { 24'h00, i_wb_data[15: 8] };
 
                4'b1111: o_result = { 24'h00, i_wb_data[ 7: 0] };
 
                4'b100?: o_result = { 16'h00, i_wb_data[31:16] };
 
                4'b101?: o_result = { 16'h00, i_wb_data[15: 0] };
 
                default: o_result = i_wb_data[31:0];
 
                endcase
 
 
        assign  o_pipe_stalled = (cyc)
        assign  o_pipe_stalled = (cyc)
                        &&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
                        &&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
 
 
        generate
        generate
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                initial lock_gbl = 1'b0;
                initial lock_gbl = 1'b0;
                initial lock_lcl = 1'b0;
                initial lock_lcl = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                begin
                begin
                        lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
                        lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
                        lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl));
                        lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
                end
                end
 
 
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
 
 

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