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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipemem.v] - Diff between revs 49 and 56

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Rev 49 Rev 56
Line 75... Line 75...
                fifo_oreg[wraddr] <= i_oreg;
                fifo_oreg[wraddr] <= i_oreg;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_wb_err))
                if ((i_rst)||(i_wb_err))
                        wraddr <= 0;
                        wraddr <= 0;
                else if (i_pipe_stb)
                else if (i_pipe_stb)
                        wraddr <= wraddr + 1;
                        wraddr <= wraddr + 4'h1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_wb_err))
                if ((i_rst)||(i_wb_err))
                        rdaddr <= 0;
                        rdaddr <= 0;
                else if ((i_wb_ack)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl)))
                else if ((i_wb_ack)&&(cyc))
                        rdaddr <= rdaddr + 1;
                        rdaddr <= rdaddr + 4'h1;
        assign  nxt_rdaddr = rdaddr + 1;
        assign  nxt_rdaddr = rdaddr + 4'h1;
 
 
 
        reg     cyc;
        wire    gbl_stb, lcl_stb;
        wire    gbl_stb, lcl_stb;
        assign  lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
        assign  lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
        assign  gbl_stb = ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
        assign  gbl_stb = (~lcl_stb);
 
                        //= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
 
 
        initial cyc = 0;
 
        initial o_wb_cyc_lcl = 0;
 
        initial o_wb_cyc_gbl = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        o_wb_cyc_gbl <= 1'b0;
                        o_wb_cyc_gbl <= 1'b0;
                        o_wb_cyc_lcl <= 1'b0;
                        o_wb_cyc_lcl <= 1'b0;
                        o_wb_stb_gbl <= 1'b0;
                        o_wb_stb_gbl <= 1'b0;
                        o_wb_stb_lcl <= 1'b0;
                        o_wb_stb_lcl <= 1'b0;
                end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
                        cyc <= 1'b0;
 
                end else if (cyc)
                begin
                begin
                        if ((~i_wb_stall)&&(~i_pipe_stb))
                        if ((~i_wb_stall)&&(~i_pipe_stb))
                        begin
                        begin
                                o_wb_stb_gbl <= 1'b0;
                                o_wb_stb_gbl <= 1'b0;
                                o_wb_stb_lcl <= 1'b0;
                                o_wb_stb_lcl <= 1'b0;
                        end else if ((i_pipe_stb)&&(~i_wb_stall))
                        end else if ((i_pipe_stb)&&(~i_wb_stall))
                        begin
                        begin
                                o_wb_addr <= i_addr[(AW-1):0];
                                // o_wb_addr <= i_addr[(AW-1):0];
                                o_wb_data <= i_data;
                                // o_wb_data <= i_data;
                        end
                        end
 
 
                        if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
                        if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
                        begin
                        begin
                                o_wb_cyc_gbl <= 1'b0;
                                o_wb_cyc_gbl <= 1'b0;
                                o_wb_cyc_lcl <= 1'b0;
                                o_wb_cyc_lcl <= 1'b0;
 
                                cyc <= 1'b0;
                        end
                        end
                end else if (i_pipe_stb) // New memory operation
                end else if (i_pipe_stb) // New memory operation
                begin // Grab the wishbone
                begin // Grab the wishbone
                        o_wb_cyc_lcl <= lcl_stb;
                        o_wb_cyc_lcl <= lcl_stb;
                        o_wb_cyc_gbl <= gbl_stb;
                        o_wb_cyc_gbl <= gbl_stb;
                        o_wb_stb_lcl <= lcl_stb;
                        o_wb_stb_lcl <= lcl_stb;
                        o_wb_stb_gbl <= gbl_stb;
                        o_wb_stb_gbl <= gbl_stb;
 
                        cyc <= 1'b1;
 
                        // o_wb_addr <= i_addr[(AW-1):0];
 
                        // o_wb_data <= i_data;
 
                        // o_wb_we <= i_op
 
                end
 
        always @(posedge i_clk)
 
                if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall))
 
                begin
 
                        o_wb_addr <= i_addr[(AW-1):0];
 
                        o_wb_data <= i_data;
 
                end else if ((~cyc)&&(i_pipe_stb))
 
                begin
                        o_wb_addr <= i_addr[(AW-1):0];
                        o_wb_addr <= i_addr[(AW-1):0];
                        o_wb_data <= i_data;
                        o_wb_data <= i_data;
                        // o_wb_we <= i_op
 
                end
                end
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_pipe_stb)
                if ((i_pipe_stb)&&(~cyc))
                                &&((~i_wb_stall)
 
                                        ||((~o_wb_cyc_gbl)&&(~o_wb_cyc_lcl))))
 
                        o_wb_we   <= i_op;
                        o_wb_we   <= i_op;
 
 
        initial o_valid = 1'b0;
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
                o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
        initial o_err = 1'b0;
        initial o_err = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
                o_err <= (cyc)&&(i_wb_err);
        assign  o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
        assign  o_busy = cyc;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wreg <= fifo_oreg[rdaddr];
                o_wreg <= fifo_oreg[rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_wb_ack)
                if (i_wb_ack)
                        o_result <= i_wb_data;
                        o_result <= i_wb_data;
 
 
        assign  o_pipe_stalled = ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
        assign  o_pipe_stalled = (cyc)
                        &&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
                        &&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
endmodule
endmodule
 
 
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