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[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Diff between revs 2 and 36

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//
//
//              The interface is fascinating.  The 'i_pc' input wire is just
//              The interface is fascinating.  The 'i_pc' input wire is just
//              a suggestion of what to load.  Other wires may be loaded
//              a suggestion of what to load.  Other wires may be loaded
//              instead. i_pc is what must be output, not necessarily input.
//              instead. i_pc is what must be output, not necessarily input.
//
//
 
//      20150919 -- Added support for the WB error signal.  When reading an
 
//              instruction results in this signal being raised, the pipefetch
 
//              module will set an illegal instruction flag to be returned to
 
//              the CPU together with the instruction.  Hence, the ZipCPU
 
//              can trap on it if necessary.
 
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
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// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
// mode which this prefetch does not support.  In non--pipelined mode, the
// mode which this prefetch does not support.  In non--pipelined mode, the
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
// or 72 clocks to fetch one instruction.
// or 72 clocks to fetch one instruction.
module  prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
module  prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
                        o_i, o_pc, o_aux, o_valid,
                        o_i, o_pc, o_aux, o_valid, o_illegal,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data);
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
        parameter               AW = 1;
        parameter               AW = 1;
        input                   i_clk, i_rst, i_ce;
        input                   i_clk, i_rst, i_ce;
        input           [31:0]   i_pc;
        input           [31:0]   i_pc;
        input   [(AW-1):0]       i_aux;
        input   [(AW-1):0]       i_aux;
        output  reg     [31:0]   o_i;
        output  reg     [31:0]   o_i;
        output  reg     [31:0]   o_pc;
        output  reg     [31:0]   o_pc;
        output  reg [(AW-1):0]   o_aux;
        output  reg [(AW-1):0]   o_aux;
        output  wire            o_valid;
        output  wire            o_valid, o_illegal;
        // Wishbone outputs
        // Wishbone outputs
        output  reg             o_wb_cyc, o_wb_stb;
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  wire            o_wb_we;
        output  reg     [31:0]   o_wb_addr;
        output  reg     [31:0]   o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        // And return inputs
        // And return inputs
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 
        assign  o_wb_we = 1'b0;
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 32'h0000;
        assign  o_wb_data = 32'h0000;
 
 
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        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        o_pc <= o_wb_addr;
                        o_pc <= o_wb_addr;
 
 
        assign o_valid = (i_pc == o_pc)&&(i_aux == o_aux)&&(~o_wb_cyc);
        assign o_valid = (i_pc == o_pc)&&(i_aux == o_aux)&&(~o_wb_cyc);
 
        assign o_illegal = (o_wb_cyc)&&(i_wb_err);
 
 
endmodule
endmodule
 
 
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