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[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Diff between revs 36 and 48

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Rev 36 Rev 48
Line 49... Line 49...
// or 72 clocks to fetch one instruction.
// or 72 clocks to fetch one instruction.
module  prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
module  prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
                        o_i, o_pc, o_aux, o_valid, o_illegal,
                        o_i, o_pc, o_aux, o_valid, o_illegal,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
        parameter               AW = 1;
        parameter               ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
        input                   i_clk, i_rst, i_ce;
        input                   i_clk, i_rst, i_ce;
        input           [31:0]   i_pc;
        input           [(AW-1):0]       i_pc;
        input   [(AW-1):0]       i_aux;
        input   [(AUX_WIDTH-1):0]        i_aux;
        output  reg     [31:0]   o_i;
        output  reg     [31:0]   o_i;
        output  reg     [31:0]   o_pc;
        output  reg     [(AW-1):0]       o_pc;
        output  reg [(AW-1):0]   o_aux;
        output  reg [(AUX_WIDTH-1):0]    o_aux;
        output  wire            o_valid, o_illegal;
        output  wire            o_valid, o_illegal;
        // Wishbone outputs
        // Wishbone outputs
        output  reg             o_wb_cyc, o_wb_stb;
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  wire            o_wb_we;
        output  reg     [31:0]   o_wb_addr;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        // And return inputs
        // And return inputs
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
 
 

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