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[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Diff between revs 48 and 63

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Rev 48 Rev 63
Line 76... Line 76...
        // pipeline this, but for now let's just do one at a time.
        // pipeline this, but for now let's just do one at a time.
        initial o_wb_cyc = 1'b0;
        initial o_wb_cyc = 1'b0;
        initial o_wb_stb = 1'b0;
        initial o_wb_stb = 1'b0;
        initial o_wb_addr= 0;
        initial o_wb_addr= 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if ((i_rst)||(i_wb_ack))
                begin
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_cyc <= 1'b0;
                        if (o_wb_cyc)
                        o_wb_stb <= 1'b0;
                                o_wb_addr <= 0;
 
                end else if ((i_ce)&&(~o_wb_cyc)&&(o_wb_addr == i_pc))
 
                begin // Single value cache check
 
                        o_aux   <= i_aux;
 
                        // o_i was already set during the last bus cycle
 
                end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
                end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
                begin
                begin
                        o_wb_cyc <= 1'b1;
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        o_wb_stb <= 1'b1;
                        o_wb_addr <= i_pc;
 
                        o_aux   <= i_aux;
 
                end else if (o_wb_cyc) // Independent of ce
                end else if (o_wb_cyc) // Independent of ce
                begin
                begin
                        if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                        if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                                o_wb_stb <= 1'b0;
                                o_wb_stb <= 1'b0;
                        if (i_wb_ack)
                        if (i_wb_ack)
                                o_wb_cyc <= 1'b0;
                                o_wb_cyc <= 1'b0;
                end
                end
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
 
                if (i_rst) // Set the address to guarantee the result is invalid
 
                        o_wb_addr <= 1'b0;
 
                else if ((i_ce)&&(~o_wb_cyc))
 
                        o_wb_addr <= i_pc;
 
        always @(posedge i_clk)
 
                if ((o_wb_cyc)&&(i_wb_ack))
 
                        o_aux <= i_aux;
 
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        o_i <= i_wb_data;
                        o_i <= i_wb_data;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        o_pc <= o_wb_addr;
                        o_pc <= o_wb_addr;

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