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[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Diff between revs 48 and 63
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| Rev 48 |
Rev 63 |
| Line 76... |
Line 76... |
// pipeline this, but for now let's just do one at a time.
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// pipeline this, but for now let's just do one at a time.
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initial o_wb_cyc = 1'b0;
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initial o_wb_cyc = 1'b0;
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initial o_wb_stb = 1'b0;
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initial o_wb_stb = 1'b0;
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initial o_wb_addr= 0;
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initial o_wb_addr= 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if ((i_rst)||(i_wb_ack))
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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if (o_wb_cyc)
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o_wb_stb <= 1'b0;
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o_wb_addr <= 0;
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end else if ((i_ce)&&(~o_wb_cyc)&&(o_wb_addr == i_pc))
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begin // Single value cache check
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o_aux <= i_aux;
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// o_i was already set during the last bus cycle
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end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
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end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
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begin
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begin
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o_wb_cyc <= 1'b1;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_addr <= i_pc;
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o_aux <= i_aux;
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end else if (o_wb_cyc) // Independent of ce
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end else if (o_wb_cyc) // Independent of ce
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begin
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begin
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if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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if (i_wb_ack)
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if (i_wb_ack)
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst) // Set the address to guarantee the result is invalid
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o_wb_addr <= 1'b0;
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else if ((i_ce)&&(~o_wb_cyc))
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o_wb_addr <= i_pc;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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o_aux <= i_aux;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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o_i <= i_wb_data;
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o_i <= i_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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o_pc <= o_wb_addr;
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o_pc <= o_wb_addr;
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