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[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Diff between revs 63 and 69

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//              module will set an illegal instruction flag to be returned to
//              module will set an illegal instruction flag to be returned to
//              the CPU together with the instruction.  Hence, the ZipCPU
//              the CPU together with the instruction.  Hence, the ZipCPU
//              can trap on it if necessary.
//              can trap on it if necessary.
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
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// Flash requires a minimum of 4 clocks per byte to read, so that would be
// Flash requires a minimum of 4 clocks per byte to read, so that would be
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
// mode which this prefetch does not support.  In non--pipelined mode, the
// mode which this prefetch does not support.  In non--pipelined mode, the
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
// or 72 clocks to fetch one instruction.
// or 72 clocks to fetch one instruction.
module  prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
module  prefetch(i_clk, i_rst, i_ce, i_stalled_n, i_pc, i_aux,
                        o_i, o_pc, o_aux, o_valid, o_illegal,
                        o_i, o_pc, o_aux, o_valid, o_illegal,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
        parameter               ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
        parameter               ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
        input                           i_clk, i_rst, i_ce;
        input                           i_clk, i_rst, i_ce, i_stalled_n;
        input           [(AW-1):0]       i_pc;
        input           [(AW-1):0]       i_pc;
        input   [(AUX_WIDTH-1):0]        i_aux;
        input   [(AUX_WIDTH-1):0]        i_aux;
        output  reg     [31:0]           o_i;
        output  reg     [31:0]           o_i;
        output  reg     [(AW-1):0]       o_pc;
        output  reg     [(AW-1):0]       o_pc;
        output  reg [(AUX_WIDTH-1):0]    o_aux;
        output  reg [(AUX_WIDTH-1):0]    o_aux;
        output  wire                    o_valid, o_illegal;
        output  reg                     o_valid, o_illegal;
        // Wishbone outputs
        // Wishbone outputs
        output  reg                     o_wb_cyc, o_wb_stb;
        output  reg                     o_wb_cyc, o_wb_stb;
        output  wire                    o_wb_we;
        output  wire                    o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  wire    [31:0]           o_wb_data;
        output  wire    [31:0]           o_wb_data;
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                                o_wb_cyc <= 1'b0;
                                o_wb_cyc <= 1'b0;
                end
                end
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst) // Set the address to guarantee the result is invalid
                if (i_rst) // Set the address to guarantee the result is invalid
                        o_wb_addr <= 1'b0;
                        o_wb_addr <= {(AW){1'b1}};
                else if ((i_ce)&&(~o_wb_cyc))
                else if ((i_ce)&&(~o_wb_cyc))
                        o_wb_addr <= i_pc;
                        o_wb_addr <= i_pc;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        o_aux <= i_aux;
                        o_aux <= i_aux;
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                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        o_i <= i_wb_data;
                        o_i <= i_wb_data;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                if ((o_wb_cyc)&&(i_wb_ack))
                        o_pc <= o_wb_addr;
                        o_pc <= o_wb_addr;
 
        initial o_valid   = 1'b0;
        assign o_valid = (i_pc == o_pc)&&(i_aux == o_aux)&&(~o_wb_cyc);
        initial o_illegal = 1'b0;
        assign o_illegal = (o_wb_cyc)&&(i_wb_err);
        always @(posedge i_clk)
 
                if ((o_wb_cyc)&&(i_wb_ack))
 
                begin
 
                        o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err);
 
                        o_illegal <= i_wb_err;
 
                end else if (i_stalled_n)
 
                begin
 
                        o_valid <= 1'b0;
 
                        o_illegal <= 1'b0;
 
                end
 
 
endmodule
endmodule
 
 
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