| Line 250... |
Line 250... |
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
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wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
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wire [3:0] dcdF;
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wire [3:0] dcdF;
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wire dcdR_wr, dcdA_rd, dcdB_rd,
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wire dcdR_wr, dcdA_rd, dcdB_rd,
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dcdALU, dcdM, dcdDV, dcdFP,
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dcdALU, dcdM, dcdDV, dcdFP,
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dcdF_wr, dcd_gie, dcd_break, dcd_lock,
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dcdF_wr, dcd_gie, dcd_break, dcd_lock,
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dcd_pipe;
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dcd_pipe, dcd_ljmp;
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reg r_dcdvalid;
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reg r_dcdvalid;
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wire dcdvalid;
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wire dcdvalid;
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wire [(AW-1):0] dcd_pc;
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wire [(AW-1):0] dcd_pc;
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wire [31:0] dcdI;
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wire [31:0] dcdI;
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wire dcd_zI; // true if dcdI == 0
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wire dcd_zI; // true if dcdI == 0
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| Line 521... |
Line 521... |
initial r_dcdvalid = 1'b0;
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initial r_dcdvalid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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else if (dcd_ce)
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else if (dcd_ce)
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r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
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r_dcdvalid <= (pf_valid);
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else if ((op_ce)||(clear_pipeline))
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else if (op_ce)
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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assign dcdvalid = r_dcdvalid;
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assign dcdvalid = r_dcdvalid;
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`else // Pipe fetch
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`else // Pipe fetch
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`ifdef OPT_TRADITIONAL_PFCACHE
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`ifdef OPT_TRADITIONAL_PFCACHE
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pfcache #(LGICACHE, ADDRESS_WIDTH)
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pfcache #(LGICACHE, ADDRESS_WIDTH)
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pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
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pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
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i_clear_pf_cache,
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i_clear_pf_cache,
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// dcd_pc,
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// dcd_pc,
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~dcd_stalled,
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~dcd_stalled,
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((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
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((dcd_early_branch)&&(~clear_pipeline))
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? dcd_branch_pc:pf_pc,
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? dcd_branch_pc:pf_pc,
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instruction, instruction_pc, pf_valid,
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instruction, instruction_pc, pf_valid,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_ack, pf_stall, pf_err, i_wb_data,
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pf_ack, pf_stall, pf_err, i_wb_data,
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pf_illegal);
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pf_illegal);
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`else
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`else
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pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
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pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
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pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
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pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
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i_clear_pf_cache, ~dcd_stalled,
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i_clear_pf_cache, ~dcd_stalled,
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(new_pc)?pf_pc:dcd_branch_pc,
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(new_pc)?pf_pc:dcd_branch_pc,
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instruction, instruction_pc, pf_valid,
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instruction, instruction_pc, pf_valid,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_ack, pf_stall, pf_err, i_wb_data,
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pf_ack, pf_stall, pf_err, i_wb_data,
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| Line 563... |
Line 563... |
initial r_dcdvalid = 1'b0;
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initial r_dcdvalid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(clear_pipeline))
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if ((i_rst)||(clear_pipeline))
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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else if (dcd_ce)
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else if (dcd_ce)
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r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
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r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
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else if (op_ce)
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else if (op_ce)
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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assign dcdvalid = r_dcdvalid;
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assign dcdvalid = r_dcdvalid;
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`endif
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`endif
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| Line 583... |
Line 583... |
{ dcdB_cc, dcdB_pc, dcdB },
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{ dcdB_cc, dcdB_pc, dcdB },
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dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
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dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
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dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
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dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
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dcdR_wr,dcdA_rd, dcdB_rd,
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dcdR_wr,dcdA_rd, dcdB_rd,
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dcd_early_branch,
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dcd_early_branch,
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dcd_branch_pc,
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dcd_branch_pc, dcd_ljmp,
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dcd_pipe);
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dcd_pipe);
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`else
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`else
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idecode_deprecated
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idecode_deprecated
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#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
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#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
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IMPLEMENT_FPU)
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IMPLEMENT_FPU)
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| Line 602... |
Line 602... |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
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dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
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dcdR_wr,dcdA_rd, dcdB_rd,
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dcdR_wr,dcdA_rd, dcdB_rd,
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dcd_early_branch,
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dcd_early_branch,
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dcd_branch_pc,
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dcd_branch_pc,
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dcd_pipe);
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dcd_pipe);
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assign dcd_ljmp = 1'b0;
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`endif
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`endif
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`ifdef OPT_PIPELINED_BUS_ACCESS
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`ifdef OPT_PIPELINED_BUS_ACCESS
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reg op_pipe;
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reg op_pipe;
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| Line 734... |
Line 735... |
endcase
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endcase
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end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
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end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
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assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
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assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
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|
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wire w_opvalid;
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wire w_opvalid;
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assign w_opvalid = (~clear_pipeline)&&(dcdvalid);
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assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
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initial opvalid = 1'b0;
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initial opvalid = 1'b0;
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initial opvalid_alu = 1'b0;
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initial opvalid_alu = 1'b0;
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initial opvalid_mem = 1'b0;
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initial opvalid_mem = 1'b0;
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initial opvalid_div = 1'b0;
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initial opvalid_div = 1'b0;
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initial opvalid_fpu = 1'b0;
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initial opvalid_fpu = 1'b0;
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| Line 1555... |
Line 1556... |
else if (w_release_from_interrupt)
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else if (w_release_from_interrupt)
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pf_pc <= upc;
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pf_pc <= upc;
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else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
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else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
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pf_pc <= wr_reg_vl[(AW-1):0];
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pf_pc <= wr_reg_vl[(AW-1):0];
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`ifdef OPT_PIPELINED
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`ifdef OPT_PIPELINED
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else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
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else if ((dcd_early_branch)&&(~clear_pipeline))
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pf_pc <= dcd_branch_pc + 1;
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pf_pc <= dcd_branch_pc + 1;
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else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
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else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
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pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
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pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
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`else
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`else
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else if ((alu_pc_valid)&&(~clear_pipeline))
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else if ((alu_pc_valid)&&(~clear_pipeline))
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