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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 91 and 105

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Rev 91 Rev 105
Line 250... Line 250...
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
        wire    [3:0]    dcdF;
        wire    [3:0]    dcdF;
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
                                dcdALU, dcdM, dcdDV, dcdFP,
                                dcdALU, dcdM, dcdDV, dcdFP,
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
                                dcd_pipe;
                                dcd_pipe, dcd_ljmp;
        reg             r_dcdvalid;
        reg             r_dcdvalid;
        wire            dcdvalid;
        wire            dcdvalid;
        wire    [(AW-1):0]       dcd_pc;
        wire    [(AW-1):0]       dcd_pc;
        wire    [31:0]   dcdI;
        wire    [31:0]   dcdI;
        wire            dcd_zI; // true if dcdI == 0
        wire            dcd_zI; // true if dcdI == 0
Line 521... Line 521...
        initial r_dcdvalid = 1'b0;
        initial r_dcdvalid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
                else if (dcd_ce)
                else if (dcd_ce)
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
                        r_dcdvalid <= (pf_valid);
                else if ((op_ce)||(clear_pipeline))
                else if (op_ce)
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
        assign  dcdvalid = r_dcdvalid;
        assign  dcdvalid = r_dcdvalid;
 
 
`else // Pipe fetch
`else // Pipe fetch
 
 
`ifdef  OPT_TRADITIONAL_PFCACHE
`ifdef  OPT_TRADITIONAL_PFCACHE
        pfcache #(LGICACHE, ADDRESS_WIDTH)
        pfcache #(LGICACHE, ADDRESS_WIDTH)
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
                                        i_clear_pf_cache,
                                        i_clear_pf_cache,
                                // dcd_pc,
                                // dcd_pc,
                                ~dcd_stalled,
                                ~dcd_stalled,
                                ((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
                                ((dcd_early_branch)&&(~clear_pipeline))
                                        ? dcd_branch_pc:pf_pc,
                                        ? dcd_branch_pc:pf_pc,
                                instruction, instruction_pc, pf_valid,
                                instruction, instruction_pc, pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                pf_illegal);
                                pf_illegal);
`else
`else
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
                                        i_clear_pf_cache, ~dcd_stalled,
                                        i_clear_pf_cache, ~dcd_stalled,
                                        (new_pc)?pf_pc:dcd_branch_pc,
                                        (new_pc)?pf_pc:dcd_branch_pc,
                                        instruction, instruction_pc, pf_valid,
                                        instruction, instruction_pc, pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
                                        pf_ack, pf_stall, pf_err, i_wb_data,
Line 563... Line 563...
        initial r_dcdvalid = 1'b0;
        initial r_dcdvalid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(clear_pipeline))
                if ((i_rst)||(clear_pipeline))
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
                else if (dcd_ce)
                else if (dcd_ce)
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
                else if (op_ce)
                else if (op_ce)
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
        assign  dcdvalid = r_dcdvalid;
        assign  dcdvalid = r_dcdvalid;
`endif
`endif
 
 
Line 583... Line 583...
                        { dcdB_cc, dcdB_pc, dcdB },
                        { dcdB_cc, dcdB_pc, dcdB },
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
                        dcdR_wr,dcdA_rd, dcdB_rd,
                        dcdR_wr,dcdA_rd, dcdB_rd,
                        dcd_early_branch,
                        dcd_early_branch,
                        dcd_branch_pc,
                        dcd_branch_pc, dcd_ljmp,
                        dcd_pipe);
                        dcd_pipe);
`else
`else
        idecode_deprecated
        idecode_deprecated
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
                        IMPLEMENT_FPU)
                        IMPLEMENT_FPU)
Line 602... Line 602...
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
                        dcdR_wr,dcdA_rd, dcdB_rd,
                        dcdR_wr,dcdA_rd, dcdB_rd,
                        dcd_early_branch,
                        dcd_early_branch,
                        dcd_branch_pc,
                        dcd_branch_pc,
                        dcd_pipe);
                        dcd_pipe);
 
        assign  dcd_ljmp = 1'b0;
`endif
`endif
 
 
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        reg             op_pipe;
        reg             op_pipe;
 
 
Line 734... Line 735...
                        endcase
                        endcase
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
 
 
        wire    w_opvalid;
        wire    w_opvalid;
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid);
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
        initial opvalid     = 1'b0;
        initial opvalid     = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_mem = 1'b0;
        initial opvalid_mem = 1'b0;
        initial opvalid_div = 1'b0;
        initial opvalid_div = 1'b0;
        initial opvalid_fpu = 1'b0;
        initial opvalid_fpu = 1'b0;
Line 1555... Line 1556...
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        pf_pc <= upc;
                        pf_pc <= upc;
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                        pf_pc <= wr_reg_vl[(AW-1):0];
                        pf_pc <= wr_reg_vl[(AW-1):0];
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
                else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
                else if ((dcd_early_branch)&&(~clear_pipeline))
                        pf_pc <= dcd_branch_pc + 1;
                        pf_pc <= dcd_branch_pc + 1;
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
`else
`else
                else if ((alu_pc_valid)&&(~clear_pipeline))
                else if ((alu_pc_valid)&&(~clear_pipeline))

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