Line 302... |
Line 302... |
// PIPELINE STAGE #4 :: ALU / Memory
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// PIPELINE STAGE #4 :: ALU / Memory
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// Variable declarations
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// Variable declarations
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//
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//
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//
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//
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reg [(AW-1):0] alu_pc;
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reg [(AW-1):0] alu_pc;
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reg alu_pc_valid, mem_pc_valid;
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reg r_alu_pc_valid, mem_pc_valid;
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wire alu_pc_valid;
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wire alu_phase;
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wire alu_phase;
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wire alu_ce, alu_stall;
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wire alu_ce, alu_stall;
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wire [31:0] alu_result;
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wire [31:0] alu_result;
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wire [3:0] alu_flags;
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wire [3:0] alu_flags;
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wire alu_valid, alu_busy;
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wire alu_valid, alu_busy;
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Line 373... |
Line 374... |
//
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//
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//
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//
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// PIPELINE STAGE #2 :: Instruction Decode
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// PIPELINE STAGE #2 :: Instruction Decode
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// Calculate stall conditions
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// Calculate stall conditions
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`ifdef OPT_PIPELINED
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assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
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assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
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`else
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assign dcd_ce = 1'b1;
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`endif
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`ifdef OPT_PIPELINED
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`ifdef OPT_PIPELINED
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assign dcd_stalled = (dcdvalid)&&(op_stall);
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assign dcd_stalled = (dcdvalid)&&(op_stall);
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`else
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`else
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// If not pipelined, there will be no opvalid_ anything, and the
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// If not pipelined, there will be no opvalid_ anything, and the
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// op_stall will be false, dcdX_stall will be false, thus we can simply
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// op_stall will be false, dcdX_stall will be false, thus we can simply
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Line 426... |
Line 424... |
||(dcdF_stall)
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||(dcdF_stall)
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);
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);
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assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
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assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
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`else
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`else
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assign op_stall = (opvalid)&&(~master_ce);
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assign op_stall = (opvalid)&&(~master_ce);
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assign op_ce = ((dcdvalid)||(dcd_illegal));
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assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
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`endif
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`endif
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//
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//
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// PIPELINE STAGE #4 :: ALU / Memory
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// PIPELINE STAGE #4 :: ALU / Memory
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// Calculate stall conditions
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// Calculate stall conditions
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Line 456... |
Line 454... |
&&(~alu_stall)
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&&(~alu_stall)
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&&(~clear_pipeline);
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&&(~clear_pipeline);
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`else
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`else
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assign alu_stall = ((~master_ce)&&(opvalid_alu))
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assign alu_stall = ((~master_ce)&&(opvalid_alu))
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||((opvalid_alu)&&(op_break));
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||((opvalid_alu)&&(op_break));
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assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall);
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assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
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`endif
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`endif
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//
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//
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//
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//
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// Note: if you change the conditions for mem_ce, you must also change
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// Note: if you change the conditions for mem_ce, you must also change
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Line 471... |
Line 469... |
&&(~clear_pipeline);
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&&(~clear_pipeline);
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`else
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`else
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// If we aren't pipelined, then no one will be changing what's in the
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// If we aren't pipelined, then no one will be changing what's in the
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// pipeline (i.e. clear_pipeline), while our only instruction goes
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// pipeline (i.e. clear_pipeline), while our only instruction goes
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// through the ... pipeline.
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// through the ... pipeline.
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assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled);
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//
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// However, in hind sight this logic didn't work. What happens when
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// something gets in the pipeline and then (due to interrupt or some
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// such) needs to be voided? Thus we avoid simplification and keep
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// what worked here.
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assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
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&&(~clear_pipeline);
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`endif
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`endif
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`ifdef OPT_PIPELINED_BUS_ACCESS
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`ifdef OPT_PIPELINED_BUS_ACCESS
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assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
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assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
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(mem_pipe_stalled)
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(mem_pipe_stalled)
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||((~op_pipe)&&(mem_busy))
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||((~op_pipe)&&(mem_busy))
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Line 508... |
Line 512... |
//
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//
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//
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//
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`ifdef OPT_SINGLE_FETCH
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`ifdef OPT_SINGLE_FETCH
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wire pf_ce;
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wire pf_ce;
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assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
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assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
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prefetch #(ADDRESS_WIDTH)
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prefetch #(ADDRESS_WIDTH)
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pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
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pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
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instruction, instruction_pc, instruction_gie,
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instruction, instruction_pc, instruction_gie,
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pf_valid, pf_illegal,
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pf_valid, pf_illegal,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_ack, pf_stall, pf_err, i_wb_data);
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pf_ack, pf_stall, pf_err, i_wb_data);
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initial r_dcdvalid = 1'b0;
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initial r_dcdvalid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if ((i_rst)||(clear_pipeline))
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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else if (dcd_ce)
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else if (dcd_ce)
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r_dcdvalid <= (pf_valid);
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r_dcdvalid <= (pf_valid);
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else if (op_ce)
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else if (op_ce)
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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Line 563... |
Line 567... |
initial r_dcdvalid = 1'b0;
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initial r_dcdvalid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(clear_pipeline))
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if ((i_rst)||(clear_pipeline))
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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else if (dcd_ce)
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else if (dcd_ce)
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r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
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r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
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else if (op_ce)
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else if (op_ce)
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r_dcdvalid <= 1'b0;
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r_dcdvalid <= 1'b0;
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assign dcdvalid = r_dcdvalid;
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assign dcdvalid = r_dcdvalid;
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`endif
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`endif
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Line 621... |
Line 625... |
// However ... we need to know this before this clock, hence this is
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// However ... we need to know this before this clock, hence this is
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// calculated in the instruction decoder.
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// calculated in the instruction decoder.
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (op_ce)
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if (op_ce)
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r_op_pipe <= dcd_pipe;
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r_op_pipe <= dcd_pipe;
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else if (mem_ce) // Clear us any time an op_ is clocked in
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r_op_pipe <= 1'b0;
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assign op_pipe = r_op_pipe;
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assign op_pipe = r_op_pipe;
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`else
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`else
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assign op_pipe = 1'b0;
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assign op_pipe = 1'b0;
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`endif
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`endif
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Line 993... |
Line 999... |
// We'll use the last values from that stage
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// We'll use the last values from that stage
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// (opR_wr, opF_wr, opR) in our logic below.
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// (opR_wr, opF_wr, opR) in our logic below.
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&&((opvalid)||(mem_rdbusy)
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&&((opvalid)||(mem_rdbusy)
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||(div_busy)||(fpu_busy)||(alu_busy))
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||(div_busy)||(fpu_busy)||(alu_busy))
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&&(
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&&(
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// Stall on memory ops writing to my register
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// Okay, what happens if the result register
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// (i.e. loads), or on any write to my
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// from instruction 1 becomes the input for
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// register if I have an immediate offset
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// instruction two, *and* there's an immediate
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// Actually, this is worse. I can't tell
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// offset in instruction two? In that case, we
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// whether or not my register is going to
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// need an extra clock between the two
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// be written to, so
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// instructions to calculate the base plus
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// Note the exception for writing to the PC:
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// offset.
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// if I write to the PC, the whole next
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//
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// instruction is invalid, not just the
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// What if instruction 1 (or before) is in a
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// operand. That'll get wiped in the
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// memory pipeline? We may no longer know what
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// next operation anyway, so don't stall
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// the register was! We will then need to
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// here. This keeps a BC X, BNZ Y from
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// blindly wait. We'll temper this only waiting
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// stalling between the two branches.
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// if we're not piping this new instruction.
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// BC X, BRA Y is still clear, since BRA Y
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// If we were piping, the pipe logic in the
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// is an early branch instruction.
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// decode circuit has told us that the hazard
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// (This exception is commented out in
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// is clear, so we're okay then.
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// order to help keep our logic simple, and
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// because multiple conditional branches
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// following each other constitutes a
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// fairly unusualy code structure.)
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//
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//
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((~dcd_zI)&&(
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((~dcd_zI)&&(
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((opR == dcdB)&&(opR_wr))
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((opR == dcdB)&&(opR_wr))
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||(((opvalid_mem)||(mem_rdbusy))
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||((mem_rdbusy)&&(~dcd_pipe))
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&&(op_pipe))))
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))
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// Stall following any instruction that will
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// Stall following any instruction that will
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// set the flags, if we're going to need the
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// set the flags, if we're going to need the
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// flags (CC) register for opB.
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// flags (CC) register for opB.
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||((opF_wr)&&(dcdB_cc))
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||((opF_wr)&&(dcdB_cc))
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// Stall on any ongoing memory operation that
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// Stall on any ongoing memory operation that
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Line 1158... |
Line 1160... |
else if ((alu_ce)||(mem_ce))
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else if ((alu_ce)||(mem_ce))
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r_alu_illegal <= op_illegal;
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r_alu_illegal <= op_illegal;
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assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
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assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
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`endif
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`endif
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initial alu_pc_valid = 1'b0;
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initial r_alu_pc_valid = 1'b0;
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initial mem_pc_valid = 1'b0;
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initial mem_pc_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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alu_pc_valid <= 1'b0;
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r_alu_pc_valid <= 1'b0;
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else
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else if (alu_ce) // Includes && (~alu_clear_pipeline)
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alu_pc_valid <= (alu_ce);
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r_alu_pc_valid <= 1'b1;
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else if ((~alu_busy)||(clear_pipeline))
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r_alu_pc_valid <= 1'b0;
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assign alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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mem_pc_valid <= 1'b0;
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mem_pc_valid <= 1'b0;
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else
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else
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mem_pc_valid <= (mem_ce);
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mem_pc_valid <= (mem_ce);
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Line 1636... |
Line 1641... |
else if ((dcd_early_branch)&&(~clear_pipeline))
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else if ((dcd_early_branch)&&(~clear_pipeline))
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pf_pc <= dcd_branch_pc + 1;
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pf_pc <= dcd_branch_pc + 1;
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else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
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else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
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pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
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pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
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`else
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`else
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else if ((alu_pc_valid)&&(~clear_pipeline))
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else if ((alu_gie==gie)&&(
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((alu_pc_valid)&&(~clear_pipeline))
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||(mem_pc_valid)))
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pf_pc <= alu_pc;
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pf_pc <= alu_pc;
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`endif
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`endif
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initial new_pc = 1'b1;
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initial new_pc = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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