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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 132 and 145

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Rev 132 Rev 145
Line 302... Line 302...
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Variable declarations
        //              Variable declarations
        //
        //
        //
        //
        reg     [(AW-1):0]       alu_pc;
        reg     [(AW-1):0]       alu_pc;
        reg             alu_pc_valid, mem_pc_valid;
        reg             r_alu_pc_valid, mem_pc_valid;
 
        wire            alu_pc_valid;
        wire            alu_phase;
        wire            alu_phase;
        wire            alu_ce, alu_stall;
        wire            alu_ce, alu_stall;
        wire    [31:0]   alu_result;
        wire    [31:0]   alu_result;
        wire    [3:0]    alu_flags;
        wire    [3:0]    alu_flags;
        wire            alu_valid, alu_busy;
        wire            alu_valid, alu_busy;
Line 373... Line 374...
        //
        //
 
 
        //
        //
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Calculate stall conditions
        //              Calculate stall conditions
`ifdef  OPT_PIPELINED
 
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
`else
 
        assign          dcd_ce = 1'b1;
 
`endif
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
`else
`else
        // If not pipelined, there will be no opvalid_ anything, and the
        // If not pipelined, there will be no opvalid_ anything, and the
        // op_stall will be false, dcdX_stall will be false, thus we can simply
        // op_stall will be false, dcdX_stall will be false, thus we can simply
Line 426... Line 424...
                                ||(dcdF_stall)
                                ||(dcdF_stall)
                        );
                        );
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
`else
`else
        assign  op_stall = (opvalid)&&(~master_ce);
        assign  op_stall = (opvalid)&&(~master_ce);
        assign  op_ce = ((dcdvalid)||(dcd_illegal));
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
`endif
`endif
 
 
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Calculate stall conditions
        //              Calculate stall conditions
Line 456... Line 454...
                                &&(~alu_stall)
                                &&(~alu_stall)
                                &&(~clear_pipeline);
                                &&(~clear_pipeline);
`else
`else
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
                                ||((opvalid_alu)&&(op_break));
                                ||((opvalid_alu)&&(op_break));
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall);
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
`endif
`endif
        //
        //
 
 
        //
        //
        // Note: if you change the conditions for mem_ce, you must also change
        // Note: if you change the conditions for mem_ce, you must also change
Line 471... Line 469...
                        &&(~clear_pipeline);
                        &&(~clear_pipeline);
`else
`else
        // If we aren't pipelined, then no one will be changing what's in the
        // If we aren't pipelined, then no one will be changing what's in the
        // pipeline (i.e. clear_pipeline), while our only instruction goes
        // pipeline (i.e. clear_pipeline), while our only instruction goes
        // through the ... pipeline.
        // through the ... pipeline.
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled);
        //
 
        // However, in hind sight this logic didn't work.  What happens when
 
        // something gets in the pipeline and then (due to interrupt or some
 
        // such) needs to be voided?  Thus we avoid simplification and keep
 
        // what worked here.
 
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
 
                        &&(~clear_pipeline);
`endif
`endif
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
                                (mem_pipe_stalled)
                                (mem_pipe_stalled)
                                ||((~op_pipe)&&(mem_busy))
                                ||((~op_pipe)&&(mem_busy))
Line 508... Line 512...
        //
        //
        //
        //
`ifdef  OPT_SINGLE_FETCH
`ifdef  OPT_SINGLE_FETCH
        wire            pf_ce;
        wire            pf_ce;
 
 
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
        prefetch        #(ADDRESS_WIDTH)
        prefetch        #(ADDRESS_WIDTH)
                        pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
                        pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
                                instruction, instruction_pc, instruction_gie,
                                instruction, instruction_pc, instruction_gie,
                                        pf_valid, pf_illegal,
                                        pf_valid, pf_illegal,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
                                pf_ack, pf_stall, pf_err, i_wb_data);
                                pf_ack, pf_stall, pf_err, i_wb_data);
 
 
        initial r_dcdvalid = 1'b0;
        initial r_dcdvalid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if ((i_rst)||(clear_pipeline))
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
                else if (dcd_ce)
                else if (dcd_ce)
                        r_dcdvalid <= (pf_valid);
                        r_dcdvalid <= (pf_valid);
                else if (op_ce)
                else if (op_ce)
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
Line 563... Line 567...
        initial r_dcdvalid = 1'b0;
        initial r_dcdvalid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(clear_pipeline))
                if ((i_rst)||(clear_pipeline))
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
                else if (dcd_ce)
                else if (dcd_ce)
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
                        r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
                else if (op_ce)
                else if (op_ce)
                        r_dcdvalid <= 1'b0;
                        r_dcdvalid <= 1'b0;
        assign  dcdvalid = r_dcdvalid;
        assign  dcdvalid = r_dcdvalid;
`endif
`endif
 
 
Line 621... Line 625...
        // However ... we need to know this before this clock, hence this is
        // However ... we need to know this before this clock, hence this is
        // calculated in the instruction decoder.
        // calculated in the instruction decoder.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        r_op_pipe <= dcd_pipe;
                        r_op_pipe <= dcd_pipe;
 
                else if (mem_ce) // Clear us any time an op_ is clocked in
 
                        r_op_pipe <= 1'b0;
        assign  op_pipe = r_op_pipe;
        assign  op_pipe = r_op_pipe;
`else
`else
        assign  op_pipe = 1'b0;
        assign  op_pipe = 1'b0;
`endif
`endif
 
 
Line 993... Line 999...
                                // We'll use the last values from that stage
                                // We'll use the last values from that stage
                                // (opR_wr, opF_wr, opR) in our logic below.
                                // (opR_wr, opF_wr, opR) in our logic below.
                                &&((opvalid)||(mem_rdbusy)
                                &&((opvalid)||(mem_rdbusy)
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
                                &&(
                                &&(
                                // Stall on memory ops writing to my register
                                // Okay, what happens if the result register
                                //      (i.e. loads), or on any write to my
                                // from instruction 1 becomes the input for
                                //      register if I have an immediate offset
                                // instruction two, *and* there's an immediate
                                //      Actually, this is worse.  I can't tell
                                // offset in instruction two?  In that case, we
                                //      whether or not my register is going to
                                // need an extra clock between the two 
                                //      be written to, so 
                                // instructions to calculate the base plus 
                                // Note the exception for writing to the PC:
                                // offset.
                                //      if I write to the PC, the whole next
                                //
                                //      instruction is invalid, not just the
                                // What if instruction 1 (or before) is in a
                                //      operand.  That'll get wiped in the
                                // memory pipeline?  We may no longer know what
                                //      next operation anyway, so don't stall
                                // the register was!  We will then need  to 
                                //      here.  This keeps a BC X, BNZ Y from
                                // blindly wait.  We'll temper this only waiting
                                //      stalling between the two branches.
                                // if we're not piping this new instruction.
                                //      BC X, BRA Y is still clear, since BRA Y
                                // If we were piping, the pipe logic in the
                                //      is an early branch instruction.
                                // decode circuit has told us that the hazard
                                //      (This exception is commented out in
                                // is clear, so we're okay then.
                                //      order to help keep our logic simple, and
 
                                //      because multiple conditional branches
 
                                //      following each other constitutes a
 
                                //      fairly unusualy code structure.)
 
                                //      
                                //      
                                ((~dcd_zI)&&(
                                ((~dcd_zI)&&(
                                        ((opR == dcdB)&&(opR_wr))
                                        ((opR == dcdB)&&(opR_wr))
                                        ||(((opvalid_mem)||(mem_rdbusy))
                                        ||((mem_rdbusy)&&(~dcd_pipe))
                                        &&(op_pipe))))
                                        ))
                                // Stall following any instruction that will
                                // Stall following any instruction that will
                                // set the flags, if we're going to need the
                                // set the flags, if we're going to need the
                                // flags (CC) register for opB.
                                // flags (CC) register for opB.
                                ||((opF_wr)&&(dcdB_cc))
                                ||((opF_wr)&&(dcdB_cc))
                                // Stall on any ongoing memory operation that
                                // Stall on any ongoing memory operation that
Line 1158... Line 1160...
                else if ((alu_ce)||(mem_ce))
                else if ((alu_ce)||(mem_ce))
                        r_alu_illegal <= op_illegal;
                        r_alu_illegal <= op_illegal;
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
`endif
`endif
 
 
        initial alu_pc_valid = 1'b0;
        initial r_alu_pc_valid = 1'b0;
        initial mem_pc_valid = 1'b0;
        initial mem_pc_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        alu_pc_valid <= 1'b0;
                        r_alu_pc_valid <= 1'b0;
                else
                else if (alu_ce) // Includes && (~alu_clear_pipeline)
                        alu_pc_valid <= (alu_ce);
                        r_alu_pc_valid <= 1'b1;
 
                else if ((~alu_busy)||(clear_pipeline))
 
                        r_alu_pc_valid <= 1'b0;
 
        assign  alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy);
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        mem_pc_valid <= 1'b0;
                        mem_pc_valid <= 1'b0;
                else
                else
                        mem_pc_valid <= (mem_ce);
                        mem_pc_valid <= (mem_ce);
Line 1636... Line 1641...
                else if ((dcd_early_branch)&&(~clear_pipeline))
                else if ((dcd_early_branch)&&(~clear_pipeline))
                        pf_pc <= dcd_branch_pc + 1;
                        pf_pc <= dcd_branch_pc + 1;
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
`else
`else
                else if ((alu_pc_valid)&&(~clear_pipeline))
                else if ((alu_gie==gie)&&(
 
                                ((alu_pc_valid)&&(~clear_pipeline))
 
                                ||(mem_pc_valid)))
                        pf_pc <= alu_pc;
                        pf_pc <= alu_pc;
`endif
`endif
 
 
        initial new_pc = 1'b1;
        initial new_pc = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)

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