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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 145 and 160

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Line 69... Line 69...
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 163... Line 163...
        input                   i_halt, i_clear_pf_cache;
        input                   i_halt, i_clear_pf_cache;
        input           [4:0]    i_dbg_reg;
        input           [4:0]    i_dbg_reg;
        input                   i_dbg_we;
        input                   i_dbg_we;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
        // Debug interface -- outputs
        // Debug interface -- outputs
        output  reg             o_dbg_stall;
        output  wire            o_dbg_stall;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [3:0]    o_dbg_cc;
        output  reg     [3:0]    o_dbg_cc;
        output  wire            o_break;
        output  wire            o_break;
        // Wishbone interface -- outputs
        // Wishbone interface -- outputs
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
Line 202... Line 202...
 
 
        // Condition codes
        // Condition codes
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        reg     [3:0]    flags, iflags;
        reg     [3:0]    flags, iflags;
        wire    [13:0]   w_uflags, w_iflags;
        wire    [13:0]   w_uflags, w_iflags;
        reg             trap, break_en, step, gie, sleep;
        reg             trap, break_en, step, gie, sleep, r_halted;
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg             ill_err_u, ill_err_i;
        reg             ill_err_u, ill_err_i;
`else
`else
        wire            ill_err_u, ill_err_i;
        wire            ill_err_u, ill_err_i;
`endif
`endif
Line 282... Line 282...
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        reg             opR_wr, opR_cc, opF_wr, op_gie;
        reg             opR_wr, opR_cc, opF_wr, op_gie;
        wire    [13:0]   opFl;
        wire    [13:0]   opFl;
        reg     [5:0]    r_opF;
        reg     [5:0]    r_opF;
        wire    [7:0]    opF;
        wire    [7:0]    opF;
        wire            op_ce, op_phase, op_pipe;
        wire            op_ce, op_phase, op_pipe, op_change_data_ce;
        // Some pipeline control wires
        // Some pipeline control wires
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        reg     opA_alu, opA_mem;
        reg     opA_alu, opA_mem;
        reg     opB_alu, opB_mem;
        reg     opB_alu, opB_mem;
`endif
`endif
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg     op_illegal;
        reg     op_illegal;
 
`else
 
        wire    op_illegal;
 
        assign  op_illegal = 1'b0;
`endif
`endif
        reg     op_break;
        reg     op_break;
        wire    op_lock;
        wire    op_lock;
 
 
 
 
Line 344... Line 347...
 
 
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
                                &&(set_cond);
                                &&(set_cond);
 
 
 
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
 
        wire    adf_ce, adf_ce_unconditional;
 
        assign  adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid)
 
                                &&(~opvalid_mem)&&(~mem_rdbusy)&&(~div_busy)
 
                                &&(~fpu_busy);
 
        assign  adf_ce = (adf_ce_unconditional)&&(set_cond);
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #5 :: Write-back
        //      PIPELINE STAGE #5 :: Write-back
        //              Variable declarations
        //              Variable declarations
        //
        //
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
        wire    [4:0]    wr_reg_id;
        wire    [4:0]    wr_reg_id;
        wire    [31:0]   wr_reg_vl;
        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;
        wire    w_switch_to_interrupt, w_release_from_interrupt;
        wire    w_switch_to_interrupt, w_release_from_interrupt;
        reg     [(AW-1):0]       upc, ipc;
        reg     [(AW-1):0]       upc, ipc;
 
 
 
 
 
 
Line 422... Line 431...
                                // Or if we need to wait on flags to work on the
                                // Or if we need to wait on flags to work on the
                                // CC register
                                // CC register
                                ||(dcdF_stall)
                                ||(dcdF_stall)
                        );
                        );
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
 
        // BUT ... op_ce is too complex for many of the data operations.  So
 
        // let's make their circuit enable code simpler.  In particular, if
 
        // op_ doesn't need to be preserved, we can change it all we want
 
        // ... right?  The clear_pipeline code, for example, really only needs
 
        // to determine whether opvalid is true.
 
        assign  op_change_data_ce = (~op_stall);
`else
`else
        assign  op_stall = (opvalid)&&(~master_ce);
        assign  op_stall = (opvalid)&&(~master_ce);
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
 
        assign  op_change_data_ce = 1'b1;
`endif
`endif
 
 
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Calculate stall conditions
        //              Calculate stall conditions
Line 448... Line 464...
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                                &&(wr_write_cc)) // Case 3
                                &&(wr_write_cc)) // Case 3
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
                        ||((opvalid)&&(op_break))
                        ||((opvalid)&&(op_break))
                        ||(div_busy)||(fpu_busy);
                        ||(div_busy)||(fpu_busy);
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
                                &&(~alu_stall)
 
                                &&(~clear_pipeline);
                                &&(~clear_pipeline);
`else
`else
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
                                ||((opvalid_alu)&&(op_break));
                                ||((opvalid_alu)&&(op_break));
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
Line 711... Line 726...
                        opB_rd <= dcdB_rd;
                        opB_rd <= dcdB_rd;
                end
                end
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_change_data_ce)
                begin
                begin
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_gpreg_vl;
                        else if (dcdA_pc)
                        else if (dcdA_pc)
                                r_opA <= w_pcA_v;
                                r_opA <= w_pcA_v;
                        else if (dcdA_cc)
                        else if (dcdA_cc)
                                r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };
                                r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };
                        else
                        else
Line 727... Line 742...
                end else
                end else
                begin // We were going to pick these up when they became valid,
                begin // We were going to pick these up when they became valid,
                        // but for some reason we're stuck here as they became
                        // but for some reason we're stuck here as they became
                        // valid.  Pick them up now anyway
                        // valid.  Pick them up now anyway
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
                                // r_opA <= wr_reg_vl;
                                // r_opA <= wr_gpreg_vl;
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_gpreg_vl;
`endif
`endif
                end
                end
 
 
        wire    [31:0]   w_opBnI, w_pcB_v;
        wire    [31:0]   w_opBnI, w_pcB_v;
        generate
        generate
Line 742... Line 757...
        else
        else
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
        endgenerate
        endgenerate
 
 
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
                : ((dcdB_pc) ? w_pcB_v
                : ((dcdB_pc) ? w_pcB_v
                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
                        (dcdB[4])?w_uflags:w_iflags}
                        (dcdB[4])?w_uflags:w_iflags}
                : w_opB)));
                : w_opB)));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_change_data_ce)
                        r_opB <= w_opBnI + dcdI;
                        r_opB <= w_opBnI + dcdI;
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
                        r_opB <= wr_reg_vl;
                        r_opB <= wr_gpreg_vl;
`endif
`endif
 
 
        // The logic here has become more complex than it should be, no thanks
        // The logic here has become more complex than it should be, no thanks
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
        // be two sets of four bits: the top bits specify what bits matter, the
        // be two sets of four bits: the top bits specify what bits matter, the
Line 766... Line 781...
        // conditions checking those bits.  Therefore, Vivado complains that
        // conditions checking those bits.  Therefore, Vivado complains that
        // these two bits are redundant.  Hence the convoluted expression
        // these two bits are redundant.  Hence the convoluted expression
        // below, arriving at what we finally want in the (now wire net)
        // below, arriving at what we finally want in the (now wire net)
        // opF.
        // opF.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce) // Cannot do op_change_data_ce here since opF depends
 
                        // upon being either correct for a valid op, or correct
 
                        // for the last valid op
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                        case(dcdF[2:0])
                        case(dcdF[2:0])
                        3'h0:   r_opF <= 6'h00; // Always
                        3'h0:   r_opF <= 6'h00; // Always
`ifdef  OPT_NEW_INSTRUCTION_SET
`ifdef  OPT_NEW_INSTRUCTION_SET
                        // These were remapped as part of the new instruction
                        // These were remapped as part of the new instruction
Line 828... Line 845...
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
                        opvalid_mem <= (dcdM)&&(w_opvalid);
                        opvalid_mem <= (dcdM)&&(w_opvalid);
                        opvalid_div <= (dcdDV)&&(w_opvalid);
                        opvalid_div <= (dcdDV)&&(w_opvalid);
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
`endif
`endif
                end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
                end else if ((clear_pipeline)||(adf_ce_unconditional)||(mem_ce))
                begin
                begin
                        opvalid     <= 1'b0;
                        opvalid     <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_mem <= 1'b0;
                        opvalid_mem <= 1'b0;
                        opvalid_div <= 1'b0;
                        opvalid_div <= 1'b0;
Line 871... Line 888...
 
 
                assign  op_lock_stall = r_op_lock_stall;
                assign  op_lock_stall = r_op_lock_stall;
 
 
                initial r_op_lock = 1'b0;
                initial r_op_lock = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_rst)
                        if ((i_rst)||(clear_pipeline))
                                r_op_lock <= 1'b0;
                                r_op_lock <= 1'b0;
                        else if (op_ce)
                        else if (op_ce)
                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);
                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);
                assign  op_lock = r_op_lock;
                assign  op_lock = r_op_lock;
 
 
Line 912... Line 929...
                                &&(~dcd_early_branch)&&(~dcd_illegal);
                                &&(~dcd_early_branch)&&(~dcd_illegal);
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
                end
                end
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_change_data_ce)
                begin
                begin
                        opn    <= dcdOp;        // Which ALU operation?
                        opn    <= dcdOp;        // Which ALU operation?
                        // opM  <= dcdM;        // Is this a memory operation?
                        // opM  <= dcdM;        // Is this a memory operation?
                        // What register will these results be written into?
                        // What register will these results be written into?
                        opR    <= dcdR;
                        opR    <= dcdR;
Line 934... Line 951...
        reg     r_op_phase;
        reg     r_op_phase;
        initial r_op_phase = 1'b0;
        initial r_op_phase = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(clear_pipeline))
                if ((i_rst)||(clear_pipeline))
                        r_op_phase <= 1'b0;
                        r_op_phase <= 1'b0;
                else if (op_ce)
                else if (op_change_data_ce)
                        r_op_phase <= dcd_phase;
                        r_op_phase <= dcd_phase;
        assign  op_phase = r_op_phase;
        assign  op_phase = r_op_phase;
`else
`else
        assign  op_phase = 1'b0;
        assign  op_phase = 1'b0;
`endif
`endif
Line 955... Line 972...
        // We'll create a flag here to start our coordination.  Once we
        // We'll create a flag here to start our coordination.  Once we
        // define this flag to something other than just plain zero, then
        // define this flag to something other than just plain zero, then
        // the stalls will already be in place.
        // the stalls will already be in place.
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
                        ?  wr_reg_vl : r_opA;
                        ?  wr_gpreg_vl : r_opA;
`else
`else
        assign  opA = r_opA;
        assign  opA = r_opA;
`endif
`endif
 
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
Line 978... Line 995...
        assign  dcdA_stall = 1'b0;
        assign  dcdA_stall = 1'b0;
`endif
`endif
 
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
                        ? wr_reg_vl: r_opB;
                        ? wr_gpreg_vl: r_opB;
`else
`else
        assign  opB = r_opB;
        assign  opB = r_opB;
`endif
`endif
 
 
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
Line 1118... Line 1135...
        reg     r_alu_phase;
        reg     r_alu_phase;
        initial r_alu_phase = 1'b0;
        initial r_alu_phase = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_alu_phase <= 1'b0;
                        r_alu_phase <= 1'b0;
                else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
                else if ((adf_ce_unconditional)||(mem_ce))
                        r_alu_phase <= op_phase;
                        r_alu_phase <= op_phase;
        assign  alu_phase = r_alu_phase;
        assign  alu_phase = r_alu_phase;
`else
`else
        assign  alu_phase = 1'b0;
        assign  alu_phase = 1'b0;
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((alu_ce)||(div_ce)||(fpu_ce))
                if (adf_ce_unconditional)
                        alu_reg <= opR;
                        alu_reg <= opR;
                else if ((i_halt)&&(i_dbg_we))
                else if ((i_halt)&&(i_dbg_we))
                        alu_reg <= i_dbg_reg;
                        alu_reg <= i_dbg_reg;
 
 
        //
        //
        // DEBUG Register write access starts here
        // DEBUG Register write access starts here
        //
        //
        reg             dbgv;
        reg             dbgv;
        initial dbgv = 1'b0;
        initial dbgv = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
                dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
        reg     [31:0]   dbg_val;
        reg     [31:0]   dbg_val;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbg_val <= i_dbg_data;
                dbg_val <= i_dbg_data;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((alu_ce)||(mem_ce))
                if ((adf_ce_unconditional)||(mem_ce))
                        alu_gie  <= op_gie;
                        alu_gie  <= op_gie;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
                if ((adf_ce_unconditional)
 
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
                                &&(~mem_stalled)))
                                &&(~mem_stalled)))
                        alu_pc  <= op_pc;
                        alu_pc  <= op_pc;
 
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg     r_alu_illegal;
        reg     r_alu_illegal;
Line 1165... Line 1183...
        initial r_alu_pc_valid = 1'b0;
        initial r_alu_pc_valid = 1'b0;
        initial mem_pc_valid = 1'b0;
        initial mem_pc_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_alu_pc_valid <= 1'b0;
                        r_alu_pc_valid <= 1'b0;
                else if (alu_ce) // Includes && (~alu_clear_pipeline)
                else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
                        r_alu_pc_valid <= 1'b1;
                        r_alu_pc_valid <= 1'b1;
                else if ((~alu_busy)||(clear_pipeline))
                else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
                        r_alu_pc_valid <= 1'b0;
                        r_alu_pc_valid <= 1'b0;
        assign  alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy);
        assign  alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        mem_pc_valid <= 1'b0;
                        mem_pc_valid <= 1'b0;
                else
                else
                        mem_pc_valid <= (mem_ce);
                        mem_pc_valid <= (mem_ce);
Line 1261... Line 1279...
        //      Note that the flags needed to be checked before issuing the
        //      Note that the flags needed to be checked before issuing the
        //      bus instruction, so they don't need to be checked here.
        //      bus instruction, so they don't need to be checked here.
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      check for that here either.
        //      check for that here either.
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  wr_reg_ce = (dbgv)||(~alu_illegal)&&
        assign  wr_reg_ce = (dbgv)||(mem_valid)
                        (((alu_wr)&&(~clear_pipeline)
                                ||((~clear_pipeline)&&(~alu_illegal)
                                &&((alu_valid)||(div_valid)||(fpu_valid)))
                                        &&(((alu_wr)&&(alu_valid))
                        ||(mem_valid));
                                                ||(div_valid)||(fpu_valid)));
`else
`else
        assign  wr_reg_ce = (dbgv)||((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
        assign  wr_reg_ce = (dbgv)||(mem_valid)
 
                                ||((~clear_pipeline)
 
                                        &&(((alu_wr)&&(alu_valid))
 
                                                ||(div_valid)||(fpu_valid)));
`endif
`endif
        // Which register shall be written?
        // Which register shall be written?
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
        //              One or PC, one for CC, and one for GIE match
        //              One or PC, one for CC, and one for GIE match
        //      Note that the alu_reg is the register to write on a divide or
        //      Note that the alu_reg is the register to write on a divide or
        //      FPU operation.
        //      FPU operation.
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
        assign  wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
        // Are we writing to the CC register?
        // Are we writing to the CC register?
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
        // Are we writing to the PC?
        // Are we writing to the PC?
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        // What value to write?
        // What value to write?
        assign  wr_reg_vl = ((mem_valid) ? mem_result
        assign  wr_gpreg_vl = ((mem_valid) ? mem_result
                                :((div_valid|fpu_valid))
                                :((div_valid|fpu_valid))
                                        ? ((div_valid) ? div_result:fpu_result)
                                        ? ((div_valid) ? div_result:fpu_result)
                                :((dbgv) ? dbg_val : alu_result));
                                :((dbgv) ? dbg_val : alu_result));
 
        assign  wr_spreg_vl = ((mem_valid) ? mem_result
 
                                :((dbgv) ? dbg_val : alu_result));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (wr_reg_ce)
                if (wr_reg_ce)
                        regset[wr_reg_id] <= wr_reg_vl;
                        regset[wr_reg_id] <= wr_gpreg_vl;
 
 
        //
        //
        // Write back to the condition codes/flags register ...
        // Write back to the condition codes/flags register ...
        // When shall we write to our flags register?  alF_wr already
        // When shall we write to our flags register?  alF_wr already
        // includes the set condition ...
        // includes the set condition ...
Line 1306... Line 1329...
 
 
        // What value to write?
        // What value to write?
        always @(posedge i_clk)
        always @(posedge i_clk)
                // If explicitly writing the register itself
                // If explicitly writing the register itself
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
                        flags <= wr_reg_vl[3:0];
                        flags <= wr_gpreg_vl[3:0];
                // Otherwise if we're setting the flags from an ALU operation
                // Otherwise if we're setting the flags from an ALU operation
                else if ((wr_flags_ce)&&(alu_gie))
                else if ((wr_flags_ce)&&(alu_gie))
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
                                : alu_flags);
                                : alu_flags);
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        iflags <= wr_reg_vl[3:0];
                        iflags <= wr_gpreg_vl[3:0];
                else if ((wr_flags_ce)&&(~alu_gie))
                else if ((wr_flags_ce)&&(~alu_gie))
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
                                : alu_flags);
                                : alu_flags);
 
 
        // The 'break' enable  bit.  This bit can only be set from supervisor
        // The 'break' enable  bit.  This bit can only be set from supervisor
Line 1339... Line 1362...
        initial break_en = 1'b0;
        initial break_en = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_halt))
                if ((i_rst)||(i_halt))
                        break_en <= 1'b0;
                        break_en <= 1'b0;
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
                        break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
 
                                &&(~alu_busy)
                                &&(~div_busy)&&(~fpu_busy)
                                &&(~div_busy)&&(~fpu_busy)
                                &&(~clear_pipeline)
                                &&(~clear_pipeline)
                        ||((~alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(div_valid)&&(div_error))
                        ||((~alu_gie)&&(div_valid)&&(div_error))
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
`else
`else
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
 
                                &&(~alu_busy)&&(~div_busy)&&(~fpu_busy)
                                &&(~clear_pipeline))
                                &&(~clear_pipeline))
                        ||((~alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(bus_err))
                        ||((~alu_gie)&&(div_valid)&&(div_error))
                        ||((~alu_gie)&&(div_valid)&&(div_error))
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));
`endif
`endif
Line 1374... Line 1399...
                        // In supervisor mode, we have no protections.  The
                        // In supervisor mode, we have no protections.  The
                        // supervisor can set the sleep bit however he wants.
                        // supervisor can set the sleep bit however he wants.
                        // Well ... not quite.  Switching to user mode and
                        // Well ... not quite.  Switching to user mode and
                        // sleep mode shouold only be possible if the interrupt
                        // sleep mode shouold only be possible if the interrupt
                        // flag isn't set.
                        // flag isn't set.
                        //      Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
                        //      Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
                        //              don't set the sleep bit
                        //              don't set the sleep bit
                        //      otherwise however it would o.w. be set
                        //      otherwise however it would o.w. be set
                        sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
                        sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
                                &&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
                                &&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
                        // In user mode, however, you can only set the sleep
                        // In user mode, however, you can only set the sleep
                        // mode while remaining in user mode.  You can't switch
                        // mode while remaining in user mode.  You can't switch
                        // to sleep mode *and* supervisor mode at the same
                        // to sleep mode *and* supervisor mode at the same
                        // time, lest you halt the CPU.
                        // time, lest you halt the CPU.
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                        sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_switch_to_interrupt))
                if ((i_rst)||(w_switch_to_interrupt))
                        step <= 1'b0;
                        step <= 1'b0;
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
                        step <= wr_reg_vl[`CPU_STEP_BIT];
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
                else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
                else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
                        step <= 1'b0;
                        step <= 1'b0;
 
 
        // The GIE register.  Only interrupts can disable the interrupt register
        // The GIE register.  Only interrupts can disable the interrupt register
        assign  w_switch_to_interrupt = (gie)&&(
        assign  w_switch_to_interrupt = (gie)&&(
Line 1417... Line 1442...
                        // Same thing on a floating point error.
                        // Same thing on a floating point error.
                        ||((fpu_valid)&&(fpu_error))
                        ||((fpu_valid)&&(fpu_error))
                        //      
                        //      
                        ||(bus_err)
                        ||(bus_err)
                        // If we write to the CC register
                        // If we write to the CC register
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                        ||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        );
                        );
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
                        // Then if we write the CC register
                        // Then if we write the CC register
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
                                &&(~wr_reg_id[4])&&(wr_write_cc))
                                &&(~wr_reg_id[4])&&(wr_write_cc))
                        );
                        );
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        gie <= 1'b0;
                        gie <= 1'b0;
Line 1439... Line 1464...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        trap <= 1'b0;
                        trap <= 1'b0;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        trap <= 1'b0;
                        trap <= 1'b0;
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
                        trap <= 1'b1;
                        trap <= 1'b1;
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
                        trap <= wr_reg_vl[`CPU_TRAP_BIT];
                        trap <= wr_spreg_vl[`CPU_TRAP_BIT];
 
 
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        initial ill_err_i = 1'b0;
        initial ill_err_i = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        ill_err_i <= 1'b0;
                        ill_err_i <= 1'b0;
                // Only the debug interface can clear this bit
                // Only the debug interface can clear this bit
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
                                &&(~wr_spreg_vl[`CPU_ILL_BIT]))
                        ill_err_i <= 1'b0;
                        ill_err_i <= 1'b0;
                else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
                else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
                        ill_err_i <= 1'b1;
                        ill_err_i <= 1'b1;
        initial ill_err_u = 1'b0;
        initial ill_err_u = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 1466... Line 1491...
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        ill_err_u <= 1'b0;
                        ill_err_u <= 1'b0;
                // If the supervisor writes to this register, clearing the
                // If the supervisor writes to this register, clearing the
                // bit, then clear it
                // bit, then clear it
                else if (((~alu_gie)||(dbgv))
                else if (((~alu_gie)||(dbgv))
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
                                &&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_ILL_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        ill_err_u <= 1'b0;
                        ill_err_u <= 1'b0;
                else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
                else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
                        ill_err_u <= 1'b1;
                        ill_err_u <= 1'b1;
`else
`else
Line 1482... Line 1507...
        initial ibus_err_flag = 1'b0;
        initial ibus_err_flag = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        ibus_err_flag <= 1'b0;
                        ibus_err_flag <= 1'b0;
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
                                &&(~wr_spreg_vl[`CPU_BUSERR_BIT]))
                        ibus_err_flag <= 1'b0;
                        ibus_err_flag <= 1'b0;
                else if ((bus_err)&&(~alu_gie))
                else if ((bus_err)&&(~alu_gie))
                        ibus_err_flag <= 1'b1;
                        ibus_err_flag <= 1'b1;
        // User bus error flag -- if ever set, it will cause an interrupt to
        // User bus error flag -- if ever set, it will cause an interrupt to
        // supervisor mode.  
        // supervisor mode.  
Line 1495... Line 1520...
                if (i_rst)
                if (i_rst)
                        ubus_err_flag <= 1'b0;
                        ubus_err_flag <= 1'b0;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        ubus_err_flag <= 1'b0;
                        ubus_err_flag <= 1'b0;
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
                                &&(~wr_spreg_vl[`CPU_BUSERR_BIT])
                                &&(wr_reg_id[4])&&(wr_write_cc))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        ubus_err_flag <= 1'b0;
                        ubus_err_flag <= 1'b0;
                else if ((bus_err)&&(alu_gie))
                else if ((bus_err)&&(alu_gie))
                        ubus_err_flag <= 1'b1;
                        ubus_err_flag <= 1'b1;
 
 
Line 1514... Line 1539...
                initial r_idiv_err_flag = 1'b0;
                initial r_idiv_err_flag = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_rst)
                        if (i_rst)
                                r_idiv_err_flag <= 1'b0;
                                r_idiv_err_flag <= 1'b0;
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT]))
                                        &&(~wr_spreg_vl[`CPU_DIVERR_BIT]))
                                r_idiv_err_flag <= 1'b0;
                                r_idiv_err_flag <= 1'b0;
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
                                r_idiv_err_flag <= 1'b1;
                                r_idiv_err_flag <= 1'b1;
                // User divide (by zero) error flag -- if ever set, it will
                // User divide (by zero) error flag -- if ever set, it will
                // cause a sudden switch interrupt to supervisor mode.  
                // cause a sudden switch interrupt to supervisor mode.  
Line 1527... Line 1552...
                        if (i_rst)
                        if (i_rst)
                                r_udiv_err_flag <= 1'b0;
                                r_udiv_err_flag <= 1'b0;
                        else if (w_release_from_interrupt)
                        else if (w_release_from_interrupt)
                                r_udiv_err_flag <= 1'b0;
                                r_udiv_err_flag <= 1'b0;
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT])
                                        &&(~wr_spreg_vl[`CPU_DIVERR_BIT])
                                        &&(wr_reg_id[4])&&(wr_write_cc))
                                        &&(wr_reg_id[4])&&(wr_write_cc))
                                r_udiv_err_flag <= 1'b0;
                                r_udiv_err_flag <= 1'b0;
                        else if ((div_error)&&(alu_gie)&&(div_valid))
                        else if ((div_error)&&(alu_gie)&&(div_valid))
                                r_udiv_err_flag <= 1'b1;
                                r_udiv_err_flag <= 1'b1;
 
 
Line 1551... Line 1576...
                initial r_ifpu_err_flag = 1'b0;
                initial r_ifpu_err_flag = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_rst)
                        if (i_rst)
                                r_ifpu_err_flag <= 1'b0;
                                r_ifpu_err_flag <= 1'b0;
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT]))
                                        &&(~wr_spreg_vl[`CPU_FPUERR_BIT]))
                                r_ifpu_err_flag <= 1'b0;
                                r_ifpu_err_flag <= 1'b0;
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
                                r_ifpu_err_flag <= 1'b1;
                                r_ifpu_err_flag <= 1'b1;
                // User floating point error flag -- if ever set, it will cause
                // User floating point error flag -- if ever set, it will cause
                // a sudden switch interrupt to supervisor mode.  
                // a sudden switch interrupt to supervisor mode.  
Line 1564... Line 1589...
                        if (i_rst)
                        if (i_rst)
                                r_ufpu_err_flag <= 1'b0;
                                r_ufpu_err_flag <= 1'b0;
                        else if (w_release_from_interrupt)
                        else if (w_release_from_interrupt)
                                r_ufpu_err_flag <= 1'b0;
                                r_ufpu_err_flag <= 1'b0;
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT])
                                        &&(~wr_spreg_vl[`CPU_FPUERR_BIT])
                                        &&(wr_reg_id[4])&&(wr_write_cc))
                                        &&(wr_reg_id[4])&&(wr_write_cc))
                                r_ufpu_err_flag <= 1'b0;
                                r_ufpu_err_flag <= 1'b0;
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
                                r_ufpu_err_flag <= 1'b1;
                                r_ufpu_err_flag <= 1'b1;
 
 
Line 1610... Line 1635...
        // What happens when the pipeline has gie and ~gie instructions within
        // What happens when the pipeline has gie and ~gie instructions within
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // a non-gie instruction?
        // a non-gie instruction?
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
                        upc <= wr_reg_vl[(AW-1):0];
                        upc <= wr_spreg_vl[(AW-1):0];
                else if ((alu_gie)&&
                else if ((alu_gie)&&
                                (((alu_pc_valid)&&(~clear_pipeline))
                                (((alu_pc_valid)&&(~clear_pipeline))
                                ||(mem_pc_valid)))
                                ||(mem_pc_valid)))
                        upc <= alu_pc;
                        upc <= alu_pc;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        ipc <= RESET_ADDRESS;
                        ipc <= RESET_ADDRESS;
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
                        ipc <= wr_reg_vl[(AW-1):0];
                        ipc <= wr_spreg_vl[(AW-1):0];
                else if ((~alu_gie)&&
                else if ((~alu_gie)&&
                                (((alu_pc_valid)&&(~clear_pipeline))
                                (((alu_pc_valid)&&(~clear_pipeline))
                                ||(mem_pc_valid)))
                                ||(mem_pc_valid)))
                        ipc <= alu_pc;
                        ipc <= alu_pc;
 
 
Line 1634... Line 1659...
                else if (w_switch_to_interrupt)
                else if (w_switch_to_interrupt)
                        pf_pc <= ipc;
                        pf_pc <= ipc;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        pf_pc <= upc;
                        pf_pc <= upc;
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                        pf_pc <= wr_reg_vl[(AW-1):0];
                        pf_pc <= wr_spreg_vl[(AW-1):0];
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
                else if ((dcd_early_branch)&&(~clear_pipeline))
                else if ((dcd_early_branch)&&(~clear_pipeline))
                        pf_pc <= dcd_branch_pc + 1;
                        pf_pc <= dcd_branch_pc + 1;
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
Line 1694... Line 1719...
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_stall <= (i_halt)&&(
                r_halted <= (i_halt)&&(
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
 
                        ||(alu_busy)||(div_busy)||(fpu_busy)
                        ||((~opvalid)&&(~i_rst)&&(~dcd_illegal))
                        ||((~opvalid)&&(~i_rst)&&(~dcd_illegal))
                        ||((~dcdvalid)&&(~i_rst)&&(~pf_illegal)));
                        ||((~dcdvalid)&&(~i_rst)&&(~pf_illegal)));
 
        assign  o_dbg_stall = r_halted;
 
 
        //
        //
        //
        //
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // later evaluate how well we are doing.
        // later evaluate how well we are doing.
Line 1725... Line 1752...
                        mem_we,
                        mem_we,
                        // ((opvalid_alu)&&(alu_stall))
                        // ((opvalid_alu)&&(alu_stall))
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
                        // opA[23:20], opA[3:0],
                        // opA[23:20], opA[3:0],
                        gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
                        gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
                /*
                /*
                        i_rst, master_ce, (new_pc),
                        i_rst, master_ce, (new_pc),
                        ((dcd_early_branch)&&(dcdvalid)),
                        ((dcd_early_branch)&&(dcdvalid)),
                        pf_valid, pf_illegal,
                        pf_valid, pf_illegal,
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,

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