| Line 5... |
Line 5... |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
//
|
//
|
// Purpose: This is the top level module holding the core of the Zip CPU
|
// Purpose: This is the top level module holding the core of the Zip CPU
|
// together. The Zip CPU is designed to be as simple as possible.
|
// together. The Zip CPU is designed to be as simple as possible.
|
// (actual implementation aside ...) The instruction set is about as
|
// (actual implementation aside ...) The instruction set is about as
|
// RISC as you can get, there are only 16 instruction types supported.
|
// RISC as you can get, with only 26 instruction types currently supported.
|
|
// (There are still 8-instruction Op-Codes reserved for floating point,
|
|
// and 5 which can be used for transactions not requiring registers.)
|
// Please see the accompanying spec.pdf file for a description of these
|
// Please see the accompanying spec.pdf file for a description of these
|
// instructions.
|
// instructions.
|
//
|
//
|
// All instructions are 32-bits wide. All bus accesses, both address and
|
// All instructions are 32-bits wide. All bus accesses, both address and
|
// data, are 32-bits over a wishbone bus.
|
// data, are 32-bits over a wishbone bus.
|
| Line 24... |
Line 26... |
//
|
//
|
// 4. Apply Instruction
|
// 4. Apply Instruction
|
//
|
//
|
// 4. Write-back Results
|
// 4. Write-back Results
|
//
|
//
|
// Further information about the inner workings of this CPU may be
|
// Further information about the inner workings of this CPU, such as
|
// found in the spec.pdf file. (The documentation within this file
|
// what causes pipeline stalls, may be found in the spec.pdf file. (The
|
// had become out of date and out of sync with the spec.pdf, so look
|
// documentation within this file had become out of date and out of sync
|
// to the spec.pdf for accurate and up to date information.)
|
// with the spec.pdf, so look to the spec.pdf for accurate and up to date
|
|
// information.)
|
//
|
//
|
//
|
//
|
// In general, the pipelining is controlled by three pieces of logic
|
// In general, the pipelining is controlled by three pieces of logic
|
// per stage: _ce, _stall, and _valid. _valid means that the stage
|
// per stage: _ce, _stall, and _valid. _valid means that the stage
|
// holds a valid instruction. _ce means that the instruction from the
|
// holds a valid instruction. _ce means that the instruction from the
|
| Line 101... |
Line 104... |
//
|
//
|
//
|
//
|
//
|
//
|
`define CPU_CC_REG 4'he
|
`define CPU_CC_REG 4'he
|
`define CPU_PC_REG 4'hf
|
`define CPU_PC_REG 4'hf
|
|
`define CPU_CLRCACHE_BIT 14 // Floating point error flag, set on error
|
|
`define CPU_PHASE_BIT 13 // Floating point error flag, set on error
|
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
|
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
|
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
|
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
|
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
|
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
|
`define CPU_TRAP_BIT 9 // User TRAP has taken place
|
`define CPU_TRAP_BIT 9 // User TRAP has taken place
|
`define CPU_ILL_BIT 8 // Illegal instruction
|
`define CPU_ILL_BIT 8 // Illegal instruction
|
| Line 133... |
Line 138... |
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
, o_debug
|
, o_debug
|
`endif
|
`endif
|
);
|
);
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
|
LGICACHE=6;
|
LGICACHE=8;
|
`ifdef OPT_MULTIPLY
|
`ifdef OPT_MULTIPLY
|
parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
|
parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
|
`else
|
`else
|
parameter IMPLEMENT_MPY = 0;
|
parameter IMPLEMENT_MPY = 0;
|
`endif
|
`endif
|
| Line 201... |
Line 206... |
reg [31:0] regset [0:31];
|
reg [31:0] regset [0:31];
|
|
|
// Condition codes
|
// Condition codes
|
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
reg [3:0] flags, iflags;
|
reg [3:0] flags, iflags;
|
wire [13:0] w_uflags, w_iflags;
|
wire [14:0] w_uflags, w_iflags;
|
reg trap, break_en, step, gie, sleep, r_halted;
|
reg trap, break_en, step, gie, sleep, r_halted;
|
|
wire break_pending;
|
|
wire w_clear_icache;
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg ill_err_u, ill_err_i;
|
reg ill_err_u, ill_err_i;
|
`else
|
`else
|
wire ill_err_u, ill_err_i;
|
wire ill_err_u, ill_err_i;
|
`endif
|
`endif
|
|
reg ubreak;
|
reg ibus_err_flag, ubus_err_flag;
|
reg ibus_err_flag, ubus_err_flag;
|
wire idiv_err_flag, udiv_err_flag;
|
wire idiv_err_flag, udiv_err_flag;
|
wire ifpu_err_flag, ufpu_err_flag;
|
wire ifpu_err_flag, ufpu_err_flag;
|
wire ihalt_phase, uhalt_phase;
|
wire ihalt_phase, uhalt_phase;
|
|
|
| Line 224... |
Line 232... |
// Variable declarations
|
// Variable declarations
|
//
|
//
|
reg [(AW-1):0] pf_pc;
|
reg [(AW-1):0] pf_pc;
|
reg new_pc;
|
reg new_pc;
|
wire clear_pipeline;
|
wire clear_pipeline;
|
assign clear_pipeline = new_pc || i_clear_pf_cache;
|
assign clear_pipeline = new_pc;
|
|
|
wire dcd_stalled;
|
wire dcd_stalled;
|
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
|
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
|
wire [(AW-1):0] pf_addr;
|
wire [(AW-1):0] pf_addr;
|
wire [31:0] pf_data;
|
wire [31:0] pf_data;
|
| Line 272... |
Line 280... |
//
|
//
|
//
|
//
|
//
|
//
|
// Now, let's read our operands
|
// Now, let's read our operands
|
reg [4:0] alu_reg;
|
reg [4:0] alu_reg;
|
reg [3:0] opn;
|
wire [3:0] opn;
|
reg [4:0] opR;
|
wire [4:0] opR;
|
reg [31:0] r_opA, r_opB;
|
reg [31:0] r_opA, r_opB;
|
reg [(AW-1):0] op_pc;
|
reg [(AW-1):0] op_pc;
|
wire [31:0] w_opA, w_opB;
|
wire [31:0] w_opA, w_opB;
|
wire [31:0] opA_nowait, opB_nowait, opA, opB;
|
wire [31:0] opA_nowait, opB_nowait, opA, opB;
|
reg opR_wr, opR_cc, opF_wr, op_gie;
|
reg opR_wr, opF_wr;
|
wire [13:0] opFl;
|
wire op_gie, opR_cc;
|
|
wire [14:0] opFl;
|
reg [5:0] r_opF;
|
reg [5:0] r_opF;
|
wire [7:0] opF;
|
wire [7:0] opF;
|
wire op_ce, op_phase, op_pipe, op_change_data_ce;
|
wire op_ce, op_phase, op_pipe, op_change_data_ce;
|
// Some pipeline control wires
|
// Some pipeline control wires
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
| Line 294... |
Line 303... |
reg op_illegal;
|
reg op_illegal;
|
`else
|
`else
|
wire op_illegal;
|
wire op_illegal;
|
assign op_illegal = 1'b0;
|
assign op_illegal = 1'b0;
|
`endif
|
`endif
|
reg op_break;
|
wire op_break;
|
wire op_lock;
|
wire op_lock;
|
|
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
//
|
//
|
reg [(AW-1):0] alu_pc;
|
wire [(AW-1):0] alu_pc;
|
reg r_alu_pc_valid, mem_pc_valid;
|
reg r_alu_pc_valid, mem_pc_valid;
|
wire alu_pc_valid;
|
wire alu_pc_valid;
|
wire alu_phase;
|
wire alu_phase;
|
wire alu_ce, alu_stall;
|
wire alu_ce, alu_stall;
|
wire [31:0] alu_result;
|
wire [31:0] alu_result;
|
wire [3:0] alu_flags;
|
wire [3:0] alu_flags;
|
wire alu_valid, alu_busy;
|
wire alu_valid, alu_busy;
|
wire set_cond;
|
wire set_cond;
|
reg alu_wr, alF_wr, alu_gie;
|
reg alu_wr, alF_wr;
|
wire alu_illegal_op;
|
wire alu_gie, alu_illegal_op, alu_illegal;
|
wire alu_illegal;
|
|
|
|
|
|
|
|
wire mem_ce, mem_stalled;
|
wire mem_ce, mem_stalled;
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
| Line 347... |
Line 355... |
|
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
&&(set_cond);
|
&&(set_cond);
|
|
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
|
wire adf_ce_unconditional;
|
wire adf_ce, adf_ce_unconditional;
|
|
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid)
|
|
&&(~opvalid_mem)&&(~mem_rdbusy)&&(~div_busy)
|
|
&&(~fpu_busy);
|
|
assign adf_ce = (adf_ce_unconditional)&&(set_cond);
|
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #5 :: Write-back
|
// PIPELINE STAGE #5 :: Write-back
|
// Variable declarations
|
// Variable declarations
|
//
|
//
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
|
|
wr_write_scc, wr_write_ucc;
|
wire [4:0] wr_reg_id;
|
wire [4:0] wr_reg_id;
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
reg [(AW-1):0] upc, ipc;
|
reg [(AW-1):0] upc, ipc;
|
|
|
| Line 398... |
Line 402... |
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands
|
// PIPELINE STAGE #3 :: Read Operands
|
// Calculate stall conditions
|
// Calculate stall conditions
|
wire op_lock_stall;
|
wire op_lock_stall;
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
|
reg cc_invalid_for_dcd;
|
|
always @(posedge i_clk)
|
|
cc_invalid_for_dcd <= (wr_flags_ce)
|
|
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)
|
|
||(opvalid)&&((opF_wr)||((opR_wr)&&(opR[3:0] == `CPU_CC_REG)))
|
|
||((alF_wr)||((alu_wr)&&(alu_reg[3:0] == `CPU_CC_REG)))
|
|
||(mem_busy)||(div_busy)||(fpu_busy);
|
|
|
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
|
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
|
// Stall if we're stopped, and not allowed to execute
|
// Stall if we're stopped, and not allowed to execute
|
// an instruction
|
// an instruction
|
// (~master_ce) // Already captured in alu_stall
|
// (~master_ce) // Already captured in alu_stall
|
//
|
//
|
| Line 416... |
Line 428... |
//
|
//
|
// Stall if we are going into memory with an operation
|
// Stall if we are going into memory with an operation
|
// that cannot be pipelined, and the memory is
|
// that cannot be pipelined, and the memory is
|
// already busy
|
// already busy
|
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
|
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
|
|
||(opR_cc)
|
)
|
)
|
||(dcdvalid)&&(
|
||(dcdvalid)&&(
|
// Stall if we need to wait for an operand A
|
// Stall if we need to wait for an operand A
|
// to be ready to read
|
// to be ready to read
|
(dcdA_stall)
|
(dcdA_stall)
|
| Line 431... |
Line 444... |
// Or if we need to wait on flags to work on the
|
// Or if we need to wait on flags to work on the
|
// CC register
|
// CC register
|
||(dcdF_stall)
|
||(dcdF_stall)
|
);
|
);
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
|
|
|
|
|
// BUT ... op_ce is too complex for many of the data operations. So
|
// BUT ... op_ce is too complex for many of the data operations. So
|
// let's make their circuit enable code simpler. In particular, if
|
// let's make their circuit enable code simpler. In particular, if
|
// op_ doesn't need to be preserved, we can change it all we want
|
// op_ doesn't need to be preserved, we can change it all we want
|
// ... right? The clear_pipeline code, for example, really only needs
|
// ... right? The clear_pipeline code, for example, really only needs
|
// to determine whether opvalid is true.
|
// to determine whether opvalid is true.
|
| Line 458... |
Line 473... |
// 4. Last case: Stall if we would otherwise move a break instruction
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
// through the ALU. Break instructions are not allowed through
|
// through the ALU. Break instructions are not allowed through
|
// the ALU.
|
// the ALU.
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
|
// Old case #3--this isn't an ALU stall though ...
|
|
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
|
&&(wr_write_cc)) // Case 3
|
|
||((opvalid)&&(op_lock)&&(op_lock_stall))
|
||((opvalid)&&(op_lock)&&(op_lock_stall))
|
||((opvalid)&&(op_break))
|
||((opvalid)&&(op_break))
|
|
||(wr_reg_ce)&&(wr_write_cc)
|
||(div_busy)||(fpu_busy);
|
||(div_busy)||(fpu_busy);
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
|
&&(~clear_pipeline);
|
&&(~clear_pipeline);
|
`else
|
`else
|
assign alu_stall = ((~master_ce)&&(opvalid_alu))
|
assign alu_stall = (opvalid_alu)&&((~master_ce)||(op_break));
|
||((opvalid_alu)&&(op_break));
|
|
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
|
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
|
`endif
|
`endif
|
//
|
//
|
|
|
//
|
//
|
| Line 518... |
Line 530... |
`else
|
`else
|
assign mem_stalled = (opvalid_mem)&&(~master_ce);
|
assign mem_stalled = (opvalid_mem)&&(~master_ce);
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
|
|
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid)
|
|
&&(~opvalid_mem)&&(~mem_rdbusy)
|
|
&&((~opvalid_alu)||(~alu_stall))&&(~op_break)
|
|
&&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline);
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
//
|
//
|
| Line 540... |
Line 557... |
initial r_dcdvalid = 1'b0;
|
initial r_dcdvalid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
r_dcdvalid <= 1'b0;
|
r_dcdvalid <= 1'b0;
|
else if (dcd_ce)
|
else if (dcd_ce)
|
r_dcdvalid <= (pf_valid);
|
r_dcdvalid <= (pf_valid)||(pf_illegal);
|
else if (op_ce)
|
else if (op_ce)
|
r_dcdvalid <= 1'b0;
|
r_dcdvalid <= 1'b0;
|
assign dcdvalid = r_dcdvalid;
|
assign dcdvalid = r_dcdvalid;
|
|
|
`else // Pipe fetch
|
`else // Pipe fetch
|
|
|
`ifdef OPT_TRADITIONAL_PFCACHE
|
`ifdef OPT_TRADITIONAL_PFCACHE
|
pfcache #(LGICACHE, ADDRESS_WIDTH)
|
pfcache #(LGICACHE, ADDRESS_WIDTH)
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
i_clear_pf_cache,
|
w_clear_icache,
|
// dcd_pc,
|
// dcd_pc,
|
~dcd_stalled,
|
~dcd_stalled,
|
((dcd_early_branch)&&(~clear_pipeline))
|
((dcd_early_branch)&&(~clear_pipeline))
|
? dcd_branch_pc:pf_pc,
|
? dcd_branch_pc:pf_pc,
|
instruction, instruction_pc, pf_valid,
|
instruction, instruction_pc, pf_valid,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_illegal);
|
pf_illegal);
|
`else
|
`else
|
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
|
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
pf(i_clk, i_rst, (new_pc)||(dcd_early_branch),
|
i_clear_pf_cache, ~dcd_stalled,
|
w_clear_icache, ~dcd_stalled,
|
(new_pc)?pf_pc:dcd_branch_pc,
|
(new_pc)?pf_pc:dcd_branch_pc,
|
instruction, instruction_pc, pf_valid,
|
instruction, instruction_pc, pf_valid,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
//`ifdef OPT_PRECLEAR_BUS
|
//`ifdef OPT_PRECLEAR_BUS
|
| Line 579... |
Line 596... |
`endif
|
`endif
|
assign instruction_gie = gie;
|
assign instruction_gie = gie;
|
|
|
initial r_dcdvalid = 1'b0;
|
initial r_dcdvalid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline)||(w_clear_icache))
|
r_dcdvalid <= 1'b0;
|
r_dcdvalid <= 1'b0;
|
else if (dcd_ce)
|
else if (dcd_ce)
|
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
|
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&(~dcd_early_branch);
|
else if (op_ce)
|
else if (op_ce)
|
r_dcdvalid <= 1'b0;
|
r_dcdvalid <= 1'b0;
|
assign dcdvalid = r_dcdvalid;
|
assign dcdvalid = r_dcdvalid;
|
`endif
|
`endif
|
|
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
|
|
|
// If not pipelined, there will be no opvalid_ anything, and the
|
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
IMPLEMENT_FPU)
|
IMPLEMENT_FPU)
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
dcd_ce, dcd_stalled, instruction, instruction_gie,
|
(~dcdvalid)||(~op_stall), dcd_stalled, instruction, instruction_gie,
|
instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
dcd_illegal, dcd_pc, dcd_gie,
|
dcd_illegal, dcd_pc, dcd_gie,
|
{ dcdR_cc, dcdR_pc, dcdR },
|
{ dcdR_cc, dcdR_pc, dcdR },
|
{ dcdA_cc, dcdA_pc, dcdA },
|
{ dcdA_cc, dcdA_pc, dcdA },
|
{ dcdB_cc, dcdB_pc, dcdB },
|
{ dcdB_cc, dcdB_pc, dcdB },
|
| Line 726... |
Line 745... |
opB_rd <= dcdB_rd;
|
opB_rd <= dcdB_rd;
|
end
|
end
|
`endif
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
|
`ifdef OPT_PIPELINED
|
if (op_change_data_ce)
|
if (op_change_data_ce)
|
|
`endif
|
begin
|
begin
|
|
`ifdef OPT_PIPELINED
|
if ((wr_reg_ce)&&(wr_reg_id == dcdA))
|
if ((wr_reg_ce)&&(wr_reg_id == dcdA))
|
r_opA <= wr_gpreg_vl;
|
r_opA <= wr_gpreg_vl;
|
else if (dcdA_pc)
|
else
|
|
`endif
|
|
if (dcdA_pc)
|
r_opA <= w_pcA_v;
|
r_opA <= w_pcA_v;
|
else if (dcdA_cc)
|
else if (dcdA_cc)
|
r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };
|
r_opA <= { w_cpu_info, w_opA[22:16], 1'b0, (dcdA[4])?w_uflags:w_iflags };
|
else
|
else
|
r_opA <= w_opA;
|
r_opA <= w_opA;
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
end else
|
end else
|
begin // We were going to pick these up when they became valid,
|
begin // We were going to pick these up when they became valid,
|
| Line 757... |
Line 781... |
else
|
else
|
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
|
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
|
endgenerate
|
endgenerate
|
|
|
assign w_opBnI = (~dcdB_rd) ? 32'h00
|
assign w_opBnI = (~dcdB_rd) ? 32'h00
|
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
|
`ifdef OPT_PIPELINED
|
|
: ((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
|
|
`endif
|
: ((dcdB_pc) ? w_pcB_v
|
: ((dcdB_pc) ? w_pcB_v
|
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
|
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:16], // w_opB[31:14],
|
(dcdB[4])?w_uflags:w_iflags}
|
1'b0, (dcdB[4])?w_uflags:w_iflags}
|
: w_opB)));
|
: w_opB));
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
|
`ifdef OPT_PIPELINED
|
if (op_change_data_ce)
|
if (op_change_data_ce)
|
r_opB <= w_opBnI + dcdI;
|
r_opB <= w_opBnI + dcdI;
|
`ifdef OPT_PIPELINED
|
|
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
|
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
|
r_opB <= wr_gpreg_vl;
|
r_opB <= wr_gpreg_vl;
|
|
`else
|
|
r_opB <= w_opBnI + dcdI;
|
`endif
|
`endif
|
|
|
// The logic here has become more complex than it should be, no thanks
|
// The logic here has become more complex than it should be, no thanks
|
// to Xilinx's Vivado trying to help. The conditions are supposed to
|
// to Xilinx's Vivado trying to help. The conditions are supposed to
|
// be two sets of four bits: the top bits specify what bits matter, the
|
// be two sets of four bits: the top bits specify what bits matter, the
|
| Line 781... |
Line 809... |
// conditions checking those bits. Therefore, Vivado complains that
|
// conditions checking those bits. Therefore, Vivado complains that
|
// these two bits are redundant. Hence the convoluted expression
|
// these two bits are redundant. Hence the convoluted expression
|
// below, arriving at what we finally want in the (now wire net)
|
// below, arriving at what we finally want in the (now wire net)
|
// opF.
|
// opF.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
|
`ifdef OPT_PIPELINED
|
if (op_ce) // Cannot do op_change_data_ce here since opF depends
|
if (op_ce) // Cannot do op_change_data_ce here since opF depends
|
// upon being either correct for a valid op, or correct
|
// upon being either correct for a valid op, or correct
|
// for the last valid op
|
// for the last valid op
|
|
`endif
|
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
|
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
|
case(dcdF[2:0])
|
case(dcdF[2:0])
|
3'h0: r_opF <= 6'h00; // Always
|
3'h0: r_opF <= 6'h00; // Always
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
// These were remapped as part of the new instruction
|
// These were remapped as part of the new instruction
|
| Line 823... |
Line 853... |
if (i_rst)
|
if (i_rst)
|
begin
|
begin
|
opvalid <= 1'b0;
|
opvalid <= 1'b0;
|
opvalid_alu <= 1'b0;
|
opvalid_alu <= 1'b0;
|
opvalid_mem <= 1'b0;
|
opvalid_mem <= 1'b0;
|
|
opvalid_div <= 1'b0;
|
|
opvalid_fpu <= 1'b0;
|
end else if (op_ce)
|
end else if (op_ce)
|
begin
|
begin
|
// Do we have a valid instruction?
|
// Do we have a valid instruction?
|
// The decoder may vote to stall one of its
|
// The decoder may vote to stall one of its
|
// instructions based upon something we currently
|
// instructions based upon something we currently
|
// have in our queue. This instruction must then
|
// have in our queue. This instruction must then
|
// move forward, and get a stall cycle inserted.
|
// move forward, and get a stall cycle inserted.
|
// Hence, the test on dcd_stalled here. If we must
|
// Hence, the test on dcd_stalled here. If we must
|
// wait until our operands are valid, then we aren't
|
// wait until our operands are valid, then we aren't
|
// valid yet until then.
|
// valid yet until then.
|
opvalid<= w_opvalid;
|
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid);
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
|
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal));
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
|
`else
|
`else
|
opvalid_alu <= (dcdALU)&&(w_opvalid);
|
opvalid_alu <= (dcdALU)&&(w_opvalid);
|
| Line 863... |
Line 895... |
// break to repeat and continue upon return. To get out of this
|
// break to repeat and continue upon return. To get out of this
|
// condition, replace the break instruction with what it is supposed
|
// condition, replace the break instruction with what it is supposed
|
// to be, step through it, and then replace it back. In this fashion,
|
// to be, step through it, and then replace it back. In this fashion,
|
// a debugger can step through code.
|
// a debugger can step through code.
|
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
|
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
|
initial op_break = 1'b0;
|
`ifdef OPT_PIPELINED
|
|
reg r_op_break;
|
|
|
|
initial r_op_break = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst) op_break <= 1'b0;
|
if (i_rst) r_op_break <= 1'b0;
|
else if (op_ce) op_break <= (dcd_break);
|
else if (op_ce) r_op_break <= (dcd_break); // &&(dcdvalid)
|
else if ((clear_pipeline)||(~opvalid))
|
else if ((clear_pipeline)||(~opvalid))
|
op_break <= 1'b0;
|
r_op_break <= 1'b0;
|
|
assign op_break = r_op_break;
|
|
`else
|
|
assign op_break = dcd_break;
|
|
`endif
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
generate
|
generate
|
if (IMPLEMENT_LOCK != 0)
|
if (IMPLEMENT_LOCK != 0)
|
begin
|
begin
|
| Line 911... |
Line 950... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline))
|
if ((i_rst)||(clear_pipeline))
|
op_illegal <= 1'b0;
|
op_illegal <= 1'b0;
|
else if(op_ce)
|
else if(op_ce)
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
|
op_illegal <= (dcdvalid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)));
|
`else
|
`else
|
op_illegal <= (dcd_illegal)||(dcd_lock);
|
op_illegal <= (dcdvalid)&&((dcd_illegal)||(dcd_lock));
|
`endif
|
`endif
|
|
else if(alu_ce)
|
|
op_illegal <= 1'b0;
|
`endif
|
`endif
|
|
|
// No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
|
// No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
|
// set, dcd_early_branch will simply be a wire connected to zero and
|
// set, dcd_early_branch will simply be a wire connected to zero and
|
// this logic should just optimize.
|
// this logic should just optimize.
|
|
`ifdef OPT_PIPELINED
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
begin
|
begin
|
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
|
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
|
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
|
end
|
end
|
|
`else
|
|
always @(posedge i_clk)
|
|
begin
|
|
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
|
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
|
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
|
|
end
|
|
`endif
|
|
|
|
`ifdef OPT_PIPELINED
|
|
reg [3:0] r_opn;
|
|
reg [4:0] r_opR;
|
|
reg r_opR_cc;
|
|
reg r_op_gie;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_change_data_ce)
|
if (op_change_data_ce)
|
begin
|
begin
|
opn <= dcdOp; // Which ALU operation?
|
r_opn <= dcdOp; // Which ALU operation?
|
// opM <= dcdM; // Is this a memory operation?
|
// opM <= dcdM; // Is this a memory operation?
|
// What register will these results be written into?
|
// What register will these results be written into?
|
opR <= dcdR;
|
r_opR <= dcdR;
|
opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
|
r_opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
|
// User level (1), vs supervisor (0)/interrupts disabled
|
// User level (1), vs supervisor (0)/interrupts disabled
|
op_gie <= dcd_gie;
|
r_op_gie <= dcd_gie;
|
|
|
|
|
//
|
//
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
end
|
end
|
|
assign opn = r_opn;
|
|
assign opR = r_opR;
|
|
assign op_gie = r_op_gie;
|
|
assign opR_cc = r_opR_cc;
|
|
`else
|
|
assign opn = dcdOp;
|
|
assign opR = dcdR;
|
|
assign op_gie = dcd_gie;
|
|
// With no pipelining, there is no early branching. We keep it
|
|
always @(posedge i_clk)
|
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
|
`endif
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
|
|
`ifdef OPT_VLIW
|
`ifdef OPT_VLIW
|
reg r_op_phase;
|
reg r_op_phase;
|
initial r_op_phase = 1'b0;
|
initial r_op_phase = 1'b0;
|
| Line 987... |
Line 1054... |
// CC register
|
// CC register
|
// OR ... (No other conditions)
|
// OR ... (No other conditions)
|
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
|
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
|
&&((opvalid)||(mem_rdbusy)
|
&&((opvalid)||(mem_rdbusy)
|
||(div_busy)||(fpu_busy))
|
||(div_busy)||(fpu_busy))
|
&&((opF_wr)&&(dcdA_cc));
|
&&(((opF_wr)||(cc_invalid_for_dcd))&&(dcdA_cc))
|
|
||((dcdA_rd)&&(dcdA_cc)&&(cc_invalid_for_dcd));
|
`else
|
`else
|
// There are no pipeline hazards, if we aren't pipelined
|
// There are no pipeline hazards, if we aren't pipelined
|
assign dcdA_stall = 1'b0;
|
assign dcdA_stall = 1'b0;
|
`endif
|
`endif
|
|
|
| Line 1040... |
Line 1108... |
||((mem_rdbusy)&&(~dcd_pipe))
|
||((mem_rdbusy)&&(~dcd_pipe))
|
))
|
))
|
// Stall following any instruction that will
|
// Stall following any instruction that will
|
// set the flags, if we're going to need the
|
// set the flags, if we're going to need the
|
// flags (CC) register for opB.
|
// flags (CC) register for opB.
|
||((opF_wr)&&(dcdB_cc))
|
||(((opF_wr)||(cc_invalid_for_dcd))&&(dcdB_cc))
|
// Stall on any ongoing memory operation that
|
// Stall on any ongoing memory operation that
|
// will write to opB -- captured above
|
// will write to opB -- captured above
|
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
|
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
|
);
|
)
|
|
||((dcdB_rd)&&(dcdB_cc)&&(cc_invalid_for_dcd));
|
assign dcdF_stall = ((~dcdF[3])
|
assign dcdF_stall = ((~dcdF[3])
|
||((dcdA_rd)&&(dcdA_cc))
|
||((dcdA_rd)&&(dcdA_cc))
|
||((dcdB_rd)&&(dcdB_cc)))
|
||((dcdB_rd)&&(dcdB_cc)))
|
&&(opvalid)&&(opR_cc);
|
&&(opvalid)&&(opR_cc);
|
// &&(dcdvalid) is checked for elsewhere
|
// &&(dcdvalid) is checked for elsewhere
|
| Line 1080... |
Line 1149... |
begin
|
begin
|
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
|
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
|
opA, opB, div_busy, div_valid, div_error, div_result,
|
opA, opB, div_busy, div_valid, div_error, div_result,
|
div_flags);
|
div_flags);
|
end else begin
|
end else begin
|
assign div_error = 1'b1;
|
assign div_error = 1'b0; // Can't be high unless div_valid
|
assign div_busy = 1'b0;
|
assign div_busy = 1'b0;
|
assign div_valid = 1'b0;
|
assign div_valid = 1'b0;
|
assign div_result= 32'h00;
|
assign div_result= 32'h00;
|
assign div_flags = 4'h0;
|
assign div_flags = 4'h0;
|
end endgenerate
|
end endgenerate
|
| Line 1095... |
Line 1164... |
//
|
//
|
// sfpu thefpu(i_clk, i_rst, fpu_ce,
|
// sfpu thefpu(i_clk, i_rst, fpu_ce,
|
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
|
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
|
// fpu_flags);
|
// fpu_flags);
|
//
|
//
|
assign fpu_error = 1'b1;
|
assign fpu_error = 1'b0; // Must only be true if fpu_valid
|
assign fpu_busy = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_result= 32'h00;
|
assign fpu_result= 32'h00;
|
assign fpu_flags = 4'h0;
|
assign fpu_flags = 4'h0;
|
end else begin
|
end else begin
|
assign fpu_error = 1'b1;
|
assign fpu_error = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_busy = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_valid = 1'b0;
|
assign fpu_result= 32'h00;
|
assign fpu_result= 32'h00;
|
assign fpu_flags = 4'h0;
|
assign fpu_flags = 4'h0;
|
end endgenerate
|
end endgenerate
|
| Line 1142... |
Line 1211... |
assign alu_phase = r_alu_phase;
|
assign alu_phase = r_alu_phase;
|
`else
|
`else
|
assign alu_phase = 1'b0;
|
assign alu_phase = 1'b0;
|
`endif
|
`endif
|
|
|
|
`ifdef OPT_PIPELINED
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (adf_ce_unconditional)
|
if (adf_ce_unconditional)
|
alu_reg <= opR;
|
alu_reg <= opR;
|
else if ((i_halt)&&(i_dbg_we))
|
else if ((i_halt)&&(i_dbg_we))
|
alu_reg <= i_dbg_reg;
|
alu_reg <= i_dbg_reg;
|
|
`else
|
|
always @(posedge i_clk)
|
|
if ((i_halt)&&(i_dbg_we))
|
|
alu_reg <= i_dbg_reg;
|
|
else
|
|
alu_reg <= opR;
|
|
`endif
|
|
|
//
|
//
|
// DEBUG Register write access starts here
|
// DEBUG Register write access starts here
|
//
|
//
|
reg dbgv;
|
reg dbgv;
|
| Line 1158... |
Line 1235... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
reg [31:0] dbg_val;
|
reg [31:0] dbg_val;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbg_val <= i_dbg_data;
|
dbg_val <= i_dbg_data;
|
|
`ifdef OPT_PIPELINED
|
|
reg r_alu_gie;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((adf_ce_unconditional)||(mem_ce))
|
if ((adf_ce_unconditional)||(mem_ce))
|
alu_gie <= op_gie;
|
r_alu_gie <= op_gie;
|
|
assign alu_gie = r_alu_gie;
|
|
|
|
reg [(AW-1):0] r_alu_pc;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((adf_ce_unconditional)
|
if ((adf_ce_unconditional)
|
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
&&(~mem_stalled)))
|
&&(~mem_stalled)))
|
alu_pc <= op_pc;
|
r_alu_pc <= op_pc;
|
|
assign alu_pc = r_alu_pc;
|
|
`else
|
|
assign alu_gie = op_gie;
|
|
assign alu_pc = op_pc;
|
|
`endif
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg r_alu_illegal;
|
reg r_alu_illegal;
|
initial r_alu_illegal = 0;
|
initial r_alu_illegal = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (clear_pipeline)
|
if ((i_rst)||(clear_pipeline))
|
r_alu_illegal <= 1'b0;
|
r_alu_illegal <= 1'b0;
|
else if ((alu_ce)||(mem_ce))
|
else if (alu_ce)
|
r_alu_illegal <= op_illegal;
|
r_alu_illegal <= op_illegal;
|
|
else
|
|
r_alu_illegal <= 1'b0;
|
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
|
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
|
|
`else
|
|
assign alu_illegal = 1'b0;
|
`endif
|
`endif
|
|
|
initial r_alu_pc_valid = 1'b0;
|
initial r_alu_pc_valid = 1'b0;
|
initial mem_pc_valid = 1'b0;
|
initial mem_pc_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 1297... |
Line 1389... |
// Note that the alu_reg is the register to write on a divide or
|
// Note that the alu_reg is the register to write on a divide or
|
// FPU operation.
|
// FPU operation.
|
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
|
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
|
// Are we writing to the CC register?
|
// Are we writing to the CC register?
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
|
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
|
|
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
|
// Are we writing to the PC?
|
// Are we writing to the PC?
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
|
|
// What value to write?
|
// What value to write?
|
assign wr_gpreg_vl = ((mem_valid) ? mem_result
|
assign wr_gpreg_vl = ((mem_valid) ? mem_result
|
:((div_valid|fpu_valid))
|
:((div_valid|fpu_valid))
|
? ((div_valid) ? div_result:fpu_result)
|
? ((div_valid) ? div_result:fpu_result)
|
:((dbgv) ? dbg_val : alu_result));
|
:((dbgv) ? dbg_val : alu_result));
|
| Line 1315... |
Line 1410... |
//
|
//
|
// Write back to the condition codes/flags register ...
|
// Write back to the condition codes/flags register ...
|
// When shall we write to our flags register? alF_wr already
|
// When shall we write to our flags register? alF_wr already
|
// includes the set condition ...
|
// includes the set condition ...
|
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
|
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
|
assign w_uflags = { uhalt_phase, ufpu_err_flag,
|
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
|
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
|
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
|
1'b0, step, 1'b1, sleep,
|
ubreak, step, 1'b1, sleep,
|
((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_iflags = { ihalt_phase, ifpu_err_flag,
|
assign w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
|
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
|
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
|
break_en, 1'b0, 1'b0, sleep,
|
break_en, 1'b0, 1'b0, sleep,
|
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
|
|
|
|
// What value to write?
|
// What value to write?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// If explicitly writing the register itself
|
// If explicitly writing the register itself
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(wr_write_ucc))
|
flags <= wr_gpreg_vl[3:0];
|
flags <= wr_gpreg_vl[3:0];
|
// Otherwise if we're setting the flags from an ALU operation
|
// Otherwise if we're setting the flags from an ALU operation
|
else if ((wr_flags_ce)&&(alu_gie))
|
else if ((wr_flags_ce)&&(alu_gie))
|
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
: alu_flags);
|
: alu_flags);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(wr_write_scc))
|
iflags <= wr_gpreg_vl[3:0];
|
iflags <= wr_gpreg_vl[3:0];
|
else if ((wr_flags_ce)&&(~alu_gie))
|
else if ((wr_flags_ce)&&(~alu_gie))
|
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
: alu_flags);
|
: alu_flags);
|
|
|
| Line 1352... |
Line 1447... |
// not execute the break instruction, choosing instead to enter into
|
// not execute the break instruction, choosing instead to enter into
|
// either interrupt mode or halt first.
|
// either interrupt mode or halt first.
|
// if ((break_en) AND (break_instruction)) // user mode or not
|
// if ((break_en) AND (break_instruction)) // user mode or not
|
// HALT CPU
|
// HALT CPU
|
// else if (break_instruction) // only in user mode
|
// else if (break_instruction) // only in user mode
|
// set an interrupt flag, go to supervisor mode
|
// set an interrupt flag, set the user break bit,
|
// allow supervisor to step the CPU.
|
// go to supervisor mode, allow supervisor to step the CPU.
|
// Upon a CPU halt, any break condition will be reset. The
|
// Upon a CPU halt, any break condition will be reset. The
|
// external debugger will then need to deal with whatever
|
// external debugger will then need to deal with whatever
|
// condition has taken place.
|
// condition has taken place.
|
initial break_en = 1'b0;
|
initial break_en = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_halt))
|
if ((i_rst)||(i_halt))
|
break_en <= 1'b0;
|
break_en <= 1'b0;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
|
break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)
|
`ifdef OPT_PIPELINED
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
reg r_break_pending;
|
&&(~alu_busy)
|
|
&&(~div_busy)&&(~fpu_busy)
|
initial r_break_pending = 1'b0;
|
&&(~clear_pipeline)
|
always @(posedge i_clk)
|
||((~alu_gie)&&(bus_err))
|
if ((i_rst)||(clear_pipeline)||(~opvalid))
|
||((~alu_gie)&&(div_valid)&&(div_error))
|
r_break_pending <= 1'b0;
|
||((~alu_gie)&&(fpu_valid)&&(fpu_error))
|
else if (op_break)
|
||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
|
r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy);
|
`else
|
else
|
assign o_break = (((break_en)||(~op_gie))&&(op_break)
|
r_break_pending <= 1'b0;
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
assign break_pending = r_break_pending;
|
&&(~alu_busy)&&(~div_busy)&&(~fpu_busy)
|
`else
|
&&(~clear_pipeline))
|
assign break_pending = op_break;
|
||((~alu_gie)&&(bus_err))
|
|
||((~alu_gie)&&(div_valid)&&(div_error))
|
|
||((~alu_gie)&&(fpu_valid)&&(fpu_error));
|
|
`endif
|
`endif
|
|
|
|
|
|
assign o_break = ((break_en)||(~op_gie))&&(break_pending)
|
|
&&(~clear_pipeline)
|
|
||((~alu_gie)&&(bus_err))
|
|
||((~alu_gie)&&(div_error))
|
|
||((~alu_gie)&&(fpu_error))
|
|
||((~alu_gie)&&(alu_illegal));
|
|
|
// The sleep register. Setting the sleep register causes the CPU to
|
// The sleep register. Setting the sleep register causes the CPU to
|
// sleep until the next interrupt. Setting the sleep register within
|
// sleep until the next interrupt. Setting the sleep register within
|
// interrupt mode causes the processor to halt until a reset. This is
|
// interrupt mode causes the processor to halt until a reset. This is
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// set the sleep bit and switch to supervisor mode in the same
|
// set the sleep bit and switch to supervisor mode in the same
|
| Line 1414... |
Line 1513... |
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_switch_to_interrupt))
|
if ((i_rst)||(w_switch_to_interrupt))
|
step <= 1'b0;
|
step <= 1'b0;
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
|
else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
|
step <= 1'b0;
|
step <= 1'b0;
|
|
|
// The GIE register. Only interrupts can disable the interrupt register
|
// The GIE register. Only interrupts can disable the interrupt register
|
| Line 1427... |
Line 1526... |
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
|
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
|
// If we are stepping the CPU
|
// If we are stepping the CPU
|
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
|
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
|
// If we encounter a break instruction, if the break
|
// If we encounter a break instruction, if the break
|
// enable isn't set.
|
// enable isn't set.
|
||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
||((master_ce)&&(break_pending)&&(~break_en))
|
&&(op_break)&&(~break_en))
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
// On an illegal instruction
|
// On an illegal instruction
|
||((alu_pc_valid)&&(alu_illegal))
|
||(alu_illegal)
|
`endif
|
`endif
|
// On division by zero. If the divide isn't
|
// On division by zero. If the divide isn't
|
// implemented, div_valid and div_error will be short
|
// implemented, div_valid and div_error will be short
|
// circuited and that logic will be bypassed
|
// circuited and that logic will be bypassed
|
||((div_valid)&&(div_error))
|
||(div_error)
|
// Same thing on a floating point error.
|
// Same thing on a floating point error. Note that
|
||((fpu_valid)&&(fpu_error))
|
// fpu_error must *never* be set unless fpu_valid is
|
|
// also set as well, else this will fail.
|
|
||(fpu_error)
|
//
|
//
|
||(bus_err)
|
||(bus_err)
|
// If we write to the CC register
|
// If we write to the CC register
|
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
);
|
);
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
// Then if we write the CC register
|
// Then if we write the sCC register
|
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
&&(~wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_write_scc))
|
);
|
);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
gie <= 1'b0;
|
gie <= 1'b0;
|
else if (w_switch_to_interrupt)
|
else if (w_switch_to_interrupt)
|
| Line 1460... |
Line 1560... |
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
gie <= 1'b1;
|
gie <= 1'b1;
|
|
|
initial trap = 1'b0;
|
initial trap = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)||(w_release_from_interrupt))
|
trap <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
trap <= 1'b0;
|
trap <= 1'b0;
|
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
&&(wr_write_cc)) // &&(wr_reg_id[4]) implied
|
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
|
trap <= 1'b1;
|
trap <= 1'b1;
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
|
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
|
trap <= wr_spreg_vl[`CPU_TRAP_BIT];
|
trap <= (trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
|
|
|
|
initial ubreak = 1'b0;
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||(w_release_from_interrupt))
|
|
ubreak <= 1'b0;
|
|
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
|
|
ubreak <= 1'b1;
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
|
ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
|
|
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
initial ill_err_i = 1'b0;
|
initial ill_err_i = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ill_err_i <= 1'b0;
|
ill_err_i <= 1'b0;
|
// Only the debug interface can clear this bit
|
// Only the debug interface can clear this bit
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_spreg_vl[`CPU_ILL_BIT]))
|
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
|
ill_err_i <= 1'b0;
|
else if ((alu_illegal)&&(~alu_gie))
|
else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
|
|
ill_err_i <= 1'b1;
|
ill_err_i <= 1'b1;
|
initial ill_err_u = 1'b0;
|
initial ill_err_u = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
|
ill_err_u <= 1'b0;
|
|
// The bit is automatically cleared on release from interrupt
|
// The bit is automatically cleared on release from interrupt
|
else if (w_release_from_interrupt)
|
// or reset
|
|
if ((i_rst)||(w_release_from_interrupt))
|
ill_err_u <= 1'b0;
|
ill_err_u <= 1'b0;
|
// If the supervisor writes to this register, clearing the
|
// If the supervisor (or debugger) writes to this register,
|
// bit, then clear it
|
// clearing the bit, then clear it
|
else if (((~alu_gie)||(dbgv))
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_ILL_BIT])
|
ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
else if ((alu_illegal)&&(alu_gie))
|
ill_err_u <= 1'b0;
|
|
else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
|
|
ill_err_u <= 1'b1;
|
ill_err_u <= 1'b1;
|
`else
|
`else
|
assign ill_err_u = 1'b0;
|
assign ill_err_u = 1'b0;
|
assign ill_err_i = 1'b0;
|
assign ill_err_i = 1'b0;
|
`endif
|
`endif
|
| Line 1506... |
Line 1610... |
// ever set.
|
// ever set.
|
initial ibus_err_flag = 1'b0;
|
initial ibus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ibus_err_flag <= 1'b0;
|
ibus_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_spreg_vl[`CPU_BUSERR_BIT]))
|
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
ibus_err_flag <= 1'b0;
|
|
else if ((bus_err)&&(~alu_gie))
|
else if ((bus_err)&&(~alu_gie))
|
ibus_err_flag <= 1'b1;
|
ibus_err_flag <= 1'b1;
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// supervisor mode.
|
// supervisor mode.
|
initial ubus_err_flag = 1'b0;
|
initial ubus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)||(w_release_from_interrupt))
|
ubus_err_flag <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
ubus_err_flag <= 1'b0;
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
|
&&(~wr_spreg_vl[`CPU_BUSERR_BIT])
|
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
|
ubus_err_flag <= 1'b0;
|
ubus_err_flag <= 1'b0;
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
|
ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
else if ((bus_err)&&(alu_gie))
|
else if ((bus_err)&&(alu_gie))
|
ubus_err_flag <= 1'b1;
|
ubus_err_flag <= 1'b1;
|
|
|
generate
|
generate
|
if (IMPLEMENT_DIVIDE != 0)
|
if (IMPLEMENT_DIVIDE != 0)
|
| Line 1538... |
Line 1637... |
// to be able to tell if/why the CPU crashed.
|
// to be able to tell if/why the CPU crashed.
|
initial r_idiv_err_flag = 1'b0;
|
initial r_idiv_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_idiv_err_flag <= 1'b0;
|
r_idiv_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_spreg_vl[`CPU_DIVERR_BIT]))
|
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
r_idiv_err_flag <= 1'b0;
|
else if ((div_error)&&(~alu_gie))
|
else if ((div_error)&&(div_valid)&&(~alu_gie))
|
|
r_idiv_err_flag <= 1'b1;
|
r_idiv_err_flag <= 1'b1;
|
// User divide (by zero) error flag -- if ever set, it will
|
// User divide (by zero) error flag -- if ever set, it will
|
// cause a sudden switch interrupt to supervisor mode.
|
// cause a sudden switch interrupt to supervisor mode.
|
initial r_udiv_err_flag = 1'b0;
|
initial r_udiv_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)||(w_release_from_interrupt))
|
r_udiv_err_flag <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
r_udiv_err_flag <= 1'b0;
|
r_udiv_err_flag <= 1'b0;
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
&&(~wr_spreg_vl[`CPU_DIVERR_BIT])
|
&&(wr_write_ucc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
r_udiv_err_flag <= 1'b0;
|
else if ((div_error)&&(alu_gie))
|
else if ((div_error)&&(alu_gie)&&(div_valid))
|
|
r_udiv_err_flag <= 1'b1;
|
r_udiv_err_flag <= 1'b1;
|
|
|
assign idiv_err_flag = r_idiv_err_flag;
|
assign idiv_err_flag = r_idiv_err_flag;
|
assign udiv_err_flag = r_udiv_err_flag;
|
assign udiv_err_flag = r_udiv_err_flag;
|
end else begin
|
end else begin
|
| Line 1575... |
Line 1670... |
reg r_ifpu_err_flag, r_ufpu_err_flag;
|
reg r_ifpu_err_flag, r_ufpu_err_flag;
|
initial r_ifpu_err_flag = 1'b0;
|
initial r_ifpu_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_ifpu_err_flag <= 1'b0;
|
r_ifpu_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_write_scc))
|
&&(~wr_spreg_vl[`CPU_FPUERR_BIT]))
|
r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
|
r_ifpu_err_flag <= 1'b0;
|
|
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
|
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
|
r_ifpu_err_flag <= 1'b1;
|
r_ifpu_err_flag <= 1'b1;
|
// User floating point error flag -- if ever set, it will cause
|
// User floating point error flag -- if ever set, it will cause
|
// a sudden switch interrupt to supervisor mode.
|
// a sudden switch interrupt to supervisor mode.
|
initial r_ufpu_err_flag = 1'b0;
|
initial r_ufpu_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((i_rst)&&(w_release_from_interrupt))
|
r_ufpu_err_flag <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
r_ufpu_err_flag <= 1'b0;
|
r_ufpu_err_flag <= 1'b0;
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
&&(~wr_spreg_vl[`CPU_FPUERR_BIT])
|
&&(wr_write_ucc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
|
r_ufpu_err_flag <= 1'b0;
|
|
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
|
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
|
r_ufpu_err_flag <= 1'b1;
|
r_ufpu_err_flag <= 1'b1;
|
|
|
assign ifpu_err_flag = r_ifpu_err_flag;
|
assign ifpu_err_flag = r_ifpu_err_flag;
|
assign ufpu_err_flag = r_ufpu_err_flag;
|
assign ufpu_err_flag = r_ufpu_err_flag;
|
| Line 1608... |
Line 1699... |
reg r_ihalt_phase, r_uhalt_phase;
|
reg r_ihalt_phase, r_uhalt_phase;
|
|
|
initial r_ihalt_phase = 0;
|
initial r_ihalt_phase = 0;
|
initial r_uhalt_phase = 0;
|
initial r_uhalt_phase = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (~alu_gie)
|
if (i_rst)
|
|
r_ihalt_phase <= 1'b0;
|
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
r_ihalt_phase <= alu_phase;
|
r_ihalt_phase <= alu_phase;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (alu_gie)
|
if ((i_rst)||(w_release_from_interrupt))
|
r_uhalt_phase <= alu_phase;
|
|
else if (w_release_from_interrupt)
|
|
r_uhalt_phase <= 1'b0;
|
r_uhalt_phase <= 1'b0;
|
|
else if ((alu_gie)&&(alu_pc_valid))
|
|
r_uhalt_phase <= alu_phase;
|
|
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
|
|
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
|
|
|
assign ihalt_phase = r_ihalt_phase;
|
assign ihalt_phase = r_ihalt_phase;
|
assign uhalt_phase = r_uhalt_phase;
|
assign uhalt_phase = r_uhalt_phase;
|
`else
|
`else
|
assign ihalt_phase = 1'b0;
|
assign ihalt_phase = 1'b0;
|
| Line 1654... |
Line 1749... |
ipc <= alu_pc;
|
ipc <= alu_pc;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
pf_pc <= RESET_ADDRESS;
|
pf_pc <= RESET_ADDRESS;
|
else if (w_switch_to_interrupt)
|
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
|
pf_pc <= ipc;
|
pf_pc <= ipc;
|
else if (w_release_from_interrupt)
|
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
|
pf_pc <= upc;
|
pf_pc <= upc;
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
pf_pc <= wr_spreg_vl[(AW-1):0];
|
pf_pc <= wr_spreg_vl[(AW-1):0];
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
| Line 1685... |
Line 1780... |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else
|
else
|
new_pc <= 1'b0;
|
new_pc <= 1'b0;
|
|
|
|
`ifdef OPT_PIPELINED
|
|
reg r_clear_icache;
|
|
initial r_clear_icache = 1'b1;
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||(i_clear_pf_cache))
|
|
r_clear_icache <= 1'b1;
|
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
|
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
|
|
else
|
|
r_clear_icache <= 1'b0;
|
|
assign w_clear_icache = r_clear_icache;
|
|
`else
|
|
assign w_clear_icache = 1'b0;
|
|
`endif
|
|
|
//
|
//
|
// The debug interface
|
// The debug interface
|
generate
|
generate
|
if (AW<32)
|
if (AW<32)
|
begin
|
begin
|
| Line 1697... |
Line 1807... |
o_dbg_reg <= regset[i_dbg_reg];
|
o_dbg_reg <= regset[i_dbg_reg];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
|
o_dbg_reg[15] <= 1'b0;
|
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
end
|
end
|
end else begin
|
end else begin
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 1709... |
Line 1821... |
o_dbg_reg <= regset[i_dbg_reg];
|
o_dbg_reg <= regset[i_dbg_reg];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
|
o_dbg_reg[15] <= 1'b0;
|
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
end
|
end
|
end endgenerate
|
end endgenerate
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
|
|
|
`ifdef OPT_PIPELINED
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_halted <= (i_halt)&&(
|
r_halted <= (i_halt)&&(
|
(pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
|
// To be halted, any long lasting instruction must
|
||(alu_busy)||(div_busy)||(fpu_busy)
|
// be completed.
|
||((~opvalid)&&(~i_rst)&&(~dcd_illegal))
|
(~pf_cyc)&&(~mem_busy)&&(~alu_busy)
|
||((~dcdvalid)&&(~i_rst)&&(~pf_illegal)));
|
&&(~div_busy)&&(~fpu_busy)
|
assign o_dbg_stall = r_halted;
|
// Operations must either be valid, or illegal
|
|
&&((opvalid)||(i_rst)||(dcd_illegal))
|
|
// Decode stage must be either valid, in reset, or ill
|
|
&&((dcdvalid)||(i_rst)||(pf_illegal)));
|
|
`else
|
|
always @(posedge i_clk)
|
|
r_halted <= (i_halt)&&((opvalid)||(i_rst));
|
|
`endif
|
|
assign o_dbg_stall = ~r_halted;
|
|
|
//
|
//
|
//
|
//
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
// later evaluate how well we are doing.
|
// later evaluate how well we are doing.
|
| Line 1739... |
Line 1862... |
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
|
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_debug <= {
|
o_debug <= {
|
o_break, i_wb_err, pf_pc[1:0],
|
/*
|
flags,
|
o_break, i_wb_err, pf_pc[1:0],
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
flags,
|
op_ce, alu_ce, mem_ce,
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
//
|
op_ce, alu_ce, mem_ce,
|
master_ce, opvalid_alu, opvalid_mem,
|
//
|
//
|
master_ce, opvalid_alu, opvalid_mem,
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
//
|
mem_we,
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
// ((opvalid_alu)&&(alu_stall))
|
mem_we,
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
// ((opvalid_alu)&&(alu_stall))
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
// opA[23:20], opA[3:0],
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
|
// opA[23:20], opA[3:0],
|
|
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
|
|
*/
|
/*
|
/*
|
i_rst, master_ce, (new_pc),
|
i_rst, master_ce, (new_pc),
|
((dcd_early_branch)&&(dcdvalid)),
|
((dcd_early_branch)&&(dcdvalid)),
|
pf_valid, pf_illegal,
|
pf_valid, pf_illegal,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
|
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
|
pf_pc[7:0], pf_addr[7:0]
|
pf_pc[7:0], pf_addr[7:0]
|
*/
|
*/
|
/*
|
|
i_wb_err, gie, alu_illegal,
|
i_wb_err, gie, alu_illegal,
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
mem_busy,
|
mem_busy,
|
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
|
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
|
o_wb_addr[8:0] }
|
o_wb_addr[8:0] }
|
: { instruction[31:21] },
|
: { instruction[31:21] },
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
*/
|
|
/*
|
/*
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
|
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
|
instruction[30:27], // 4
|
instruction[30:27], // 4
|
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
|
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
|
