OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 18 and 25

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 18 Rev 25
Line 104... Line 104...
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
`define CPU_PC_REG      4'hf
 
`define CPU_CC_REG      4'he
`define CPU_CC_REG      4'he
 
`define CPU_PC_REG      4'hf
 
`define CPU_TRAP_BIT    9
`define CPU_BREAK_BIT   7
`define CPU_BREAK_BIT   7
`define CPU_STEP_BIT    6
`define CPU_STEP_BIT    6
`define CPU_GIE_BIT     5
`define CPU_GIE_BIT     5
`define CPU_SLEEP_BIT   4
`define CPU_SLEEP_BIT   4
module  zipcpu(i_clk, i_rst, i_interrupt,
module  zipcpu(i_clk, i_rst, i_interrupt,
Line 130... Line 131...
        input                   i_dbg_we;
        input                   i_dbg_we;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
        // Debug interface -- outputs
        // Debug interface -- outputs
        output  reg             o_dbg_stall;
        output  reg             o_dbg_stall;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [3:0]    o_dbg_cc;
        output  reg     [1:0]    o_dbg_cc;
        output  wire            o_break;
        output  wire            o_break;
        // Wishbone interface -- outputs
        // Wishbone interface -- outputs
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [31:0]   o_wb_addr, o_wb_data;
        output  wire    [31:0]   o_wb_addr, o_wb_data;
        // Wishbone interface -- inputs
        // Wishbone interface -- inputs
Line 148... Line 149...
 
 
        // Registers
        // Registers
        reg     [31:0]   regset [0:31];
        reg     [31:0]   regset [0:31];
 
 
        // Condition codes
        // Condition codes
        reg     [3:0]    flags, iflags;  // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        reg     [3:0]    flags, iflags;  // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        wire    [7:0]    w_uflags, w_iflags;
        wire    [9:0]    w_uflags, w_iflags;
        reg             break_en, step, gie, sleep;
        reg             trap, break_en, step, gie, sleep;
 
 
        // The master chip enable
        // The master chip enable
        wire            master_ce;
        wire            master_ce;
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //              Variable declarations
        //              Variable declarations
        //
        //
        reg     [31:0]   pf_pc;
        reg     [31:0]   pf_pc;
        reg             new_pc;
        reg             new_pc, op_break;
        wire    clear_pipeline;
        wire    clear_pipeline;
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
        assign  clear_pipeline = new_pc || i_clear_pf_cache || op_break;
 
 
        wire            dcd_stalled;
        wire            dcd_stalled;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
        wire    [31:0]   pf_addr, pf_data;
        wire    [31:0]   pf_addr, pf_data;
        wire    [31:0]   instruction, instruction_pc;
        wire    [31:0]   instruction, instruction_pc;
Line 177... Line 178...
        //
        //
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Variable declarations
        //              Variable declarations
        //
        //
        //
        //
        reg             opvalid, op_wr_pc, op_break;
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
        wire            op_stall, dcd_ce;
        wire            op_stall, dcd_ce;
        reg     [3:0]    dcdOp;
        reg     [3:0]    dcdOp;
        reg     [4:0]    dcdA, dcdB;
        reg     [4:0]    dcdA, dcdB;
 
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
        reg     [3:0]    dcdF;
        reg     [3:0]    dcdF;
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
        reg     [31:0]   dcd_pc;
        reg     [31:0]   dcd_pc;
        reg     [23:0]   r_dcdI;
        reg     [23:0]   r_dcdI;
Line 201... Line 203...
        //
        //
        // Now, let's read our operands
        // Now, let's read our operands
        reg     [4:0]    alu_reg;
        reg     [4:0]    alu_reg;
        reg     [3:0]    opn;
        reg     [3:0]    opn;
        reg     [4:0]    opR;
        reg     [4:0]    opR;
        reg     [1:0]    opA_cc, opB_cc;
 
        reg     [31:0]   r_opA, r_opB, op_pc;
        reg     [31:0]   r_opA, r_opB, op_pc;
 
        wire    [31:0]   w_opA, w_opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        reg             opR_wr, opM, opF_wr, op_gie,
        reg             opR_wr, opR_cc, opF_wr, op_gie,
                        opA_rd, opB_rd;
                        opA_rd, opB_rd;
        wire    [7:0]    opFl;
        wire    [9:0]    opFl;
        reg     [6:0]    r_opF;
        reg     [6:0]    r_opF;
        wire    [8:0]    opF;
        wire    [8:0]    opF;
        wire            op_ce;
        wire            op_ce;
 
 
 
 
Line 245... Line 247...
        //
        //
        //
        //
        //      PIPELINE STAGE #5 :: Write-back
        //      PIPELINE STAGE #5 :: Write-back
        //              Variable declarations
        //              Variable declarations
        //
        //
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc;
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
        wire    [4:0]    wr_reg_id;
        wire    [4:0]    wr_reg_id;
        wire    [31:0]   wr_reg_vl;
        wire    [31:0]   wr_reg_vl;
        wire    w_switch_to_interrupt, w_release_from_interrupt;
        wire    w_switch_to_interrupt, w_release_from_interrupt;
        reg     [31:0]   upc, ipc;
        reg     [31:0]   upc, ipc;
 
 
Line 270... Line 272...
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
        assign          dcd_stalled = (dcdvalid)&&(
        assign          dcd_stalled = (dcdvalid)&&(
                                        (op_stall)
                                        (op_stall)
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
                                        ||((opvalid)&&(op_wr_pc)));
                                        ||((opvalid)&&((op_wr_pc)||(opR_cc))));
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands
        //      PIPELINE STAGE #3 :: Read Operands
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign  op_stall = (opvalid)&&(
        assign  op_stall = ((mem_stalled)&&(opvalid_mem))
                                ((mem_stalled)&&(opM))
                                ||((alu_stall)&&(opvalid_alu));
                                ||((alu_stall)&&(~opM)));
 
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
 
 
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM))
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu))
                        ||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG }));
                        ||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
        assign  alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~clear_pipeline);
                                &&(wr_write_pc)||(wr_write_cc));
 
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
        //
        //
        assign  mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
        assign  mem_stalled = (mem_busy)||((opvalid)&&(opM)&&(
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
                                (~master_ce)
                                (~master_ce)
                                // Stall waiting for flags to be valid
                                // Stall waiting for flags to be valid
                                ||((~opF[8])&&(
                                ||((~opF[8])&&(
                                        ((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))))
                                        ((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))
                                        // Do I need this last condition?
                                        // Do I need this last condition?
                                        //||((wr_flags_ce)&&(alu_gie==op_gie))))
                                        ||(wr_flags_ce)))
                                // Or waiting for a write to the PC register
                                // Or waiting for a write to the PC register
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&(wr_write_pc))));
                                // Or CC register, since that can change the
 
                                //  PC as well
 
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
Line 342... Line 346...
                        dcdOp <= instruction[31:28];
                        dcdOp <= instruction[31:28];
 
 
                        // Default values
                        // Default values
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
 
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
 
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
 
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
 
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
                        dcdM    <= 1'b0;
                        dcdM    <= 1'b0;
                        dcdF_wr <= 1'b1;
                        dcdF_wr <= 1'b1;
                        dcd_break <= 1'b0;
 
 
 
                        // Set the condition under which we do this operation
                        // Set the condition under which we do this operation
                        // The top four bits are a mask, the bottom four the
                        // The top four bits are a mask, the bottom four the
                        // value the flags must equal once anded with the mask
                        // value the flags must equal once anded with the mask
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
Line 372... Line 379...
                                r_dcdI <= { instruction[23:0] };
                                r_dcdI <= { instruction[23:0] };
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF    <= 4'h8; // This is unconditional
                                dcdF    <= 4'h8; // This is unconditional
                                dcdOp <= 4'h2;
                                dcdOp <= 4'h2;
                                end
                                end
                        4'h4: begin // Load immediate special
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
                                dcdF_wr <= 1'b0; // Don't write flags
                                // Don't write flags except for multiplies
 
                                dcdF_wr <= (instruction[27:25] != 3'h7);
                                r_dcdI <= { 8'h00, instruction[15:0] };
                                r_dcdI <= { 8'h00, instruction[15:0] };
                                if (instruction[27:24] == 4'he)
                                if (instruction[27:24] == 4'he)
                                begin
                                begin
                                        // NOOP instruction
                                        // NOOP instruction
                                        dcdA_wr <= 1'b0;
                                        dcdA_wr <= 1'b0;
                                        dcdA_rd <= 1'b0;
                                        dcdA_rd <= 1'b0;
                                        dcdB_rd <= 1'b0;
                                        dcdB_rd <= 1'b0;
                                        dcdOp <= 4'h2;
                                        dcdOp <= 4'h2;
                                        dcd_break <= 1'b1;//Could be a break ins
 
                                end else if (instruction[27:24] == 4'hf)
                                end else if (instruction[27:24] == 4'hf)
                                begin // Load partial immediate(s)
                                begin // Load partial immediate(s)
                                        dcdA_wr <= 1'b1;
                                        dcdA_wr <= 1'b1;
                                        dcdA_rd <= 1'b1;
                                        dcdA_rd <= 1'b1;
                                        dcdB_rd <= 1'b0;
                                        dcdB_rd <= 1'b0;
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
 
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
 
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
                                        dcdOp <= { 3'h3, instruction[20] };
                                        dcdOp <= { 3'h3, instruction[20] };
                                end else begin
                                end else begin
                                        ; // Multiply instruction place holder
                                        // Actual multiply instruction
 
                                        r_dcdI <= { 8'h00, instruction[15:0] };
 
                                        dcdA_rd <= 1'b1;
 
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
 
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
                                end end
                                end end
                        4'b011?: begin // Load/Store
                        4'b011?: begin // Load/Store
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdA_wr <= (~instruction[28]); // Write on loads
                                dcdA_wr <= (~instruction[28]); // Write on loads
                                dcdA_rd <= (instruction[28]); // Read on stores
                                dcdA_rd <= (instruction[28]); // Read on stores
Line 405... Line 418...
                                else
                                else
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                                dcdM <= 1'b1; // Memory operation
                                dcdM <= 1'b1; // Memory operation
                                end
                                end
                        default: begin
                        default: begin
                                dcdA <= { instruction_gie, instruction[27:24] };
 
                                dcdB <= { instruction_gie, instruction[19:16] };
 
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
                                dcdA_rd <= 1'b1;
                                dcdA_rd <= 1'b1;
                                dcdB_rd <= instruction[20];
                                dcdB_rd <= instruction[20];
                                if (instruction[20])
                                if (instruction[20])
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
Line 420... Line 431...
                        endcase
                        endcase
 
 
 
 
                        dcd_gie <= instruction_gie;
                        dcd_gie <= instruction_gie;
                end
                end
 
        always @(posedge i_clk)
 
                if (dcd_ce)
 
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
 
                else
 
                        dcd_break <= 1'b0;
 
 
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
        //
        //
        //
        //
 
        assign  w_opA = regset[dcdA];
 
        assign  w_opB = regset[dcdB];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                begin
                begin
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_reg_vl;
                        else if (dcdA == { dcd_gie, `CPU_PC_REG })
                        else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
                                r_opA <= dcd_pc;
                                r_opA <= dcd_pc;
                        else if (dcdA[3:0] == `CPU_PC_REG)
                        else if (dcdA_pc)
                                r_opA <= (dcdA[4])?upc:ipc;
                                r_opA <= upc;
 
                        else if (dcdA_cc)
 
                                r_opA <= { w_opA[31:10], (dcd_gie)?w_uflags:w_iflags };
                        else
                        else
                                r_opA <= regset[dcdA];
                                r_opA <= w_opA;
                end
                end
        wire    [31:0]   dcdI;
        wire    [31:0]   dcdI;
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                begin
                begin
                        if (~dcdB_rd)
                        if (~dcdB_rd)
                                r_opB <= dcdI;
                                r_opB <= dcdI;
                        else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
                        else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
                                r_opB <= wr_reg_vl + dcdI;
                                r_opB <= wr_reg_vl + dcdI;
                        else if (dcdB == { dcd_gie, `CPU_PC_REG })
                        else if ((dcdB_pc)&&(dcdB[4] == dcd_gie))
                                r_opB <= dcd_pc + dcdI;
                                r_opB <= dcd_pc + dcdI;
                        else if (dcdB[3:0] == `CPU_PC_REG)
                        else if (dcdB_pc) // & dcdB[4] != dcd_gie thus is user
                                r_opB <= ((dcdB[4])?upc:ipc) + dcdI;
                                r_opB <= upc + dcdI;
 
                        else if (dcdB_cc)
 
                                r_opB <= { w_opB[31:10], (dcd_gie)?w_uflags:w_iflags} + dcdI;
                        else
                        else
                                r_opB <= regset[dcdB] + dcdI;
                                r_opB <= regset[dcdB] + dcdI;
                end
                end
 
 
        // The logic here has become more complex than it should be, no thanks
        // The logic here has become more complex than it should be, no thanks
Line 466... Line 487...
        // conditions check whether bits are on, and those are the only two
        // conditions check whether bits are on, and those are the only two
        // conditions checking those bits.  Therefore, Vivado complains that
        // conditions checking those bits.  Therefore, Vivado complains that
        // these two bits are redundant.  Hence the convoluted expression
        // these two bits are redundant.  Hence the convoluted expression
        // below, arriving at what we finally want in the (now wire net)
        // below, arriving at what we finally want in the (now wire net)
        // opF.
        // opF.
`define NEWCODE
 
`ifdef  NEWCODE
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin // Set the flag condition codes
                begin // Set the flag condition codes
                        case(dcdF[2:0])
                        case(dcdF[2:0])
                        3'h0:   r_opF <= 7'h80; // Always
                        3'h0:   r_opF <= 7'h80; // Always
Line 483... Line 502...
                        3'h6:   r_opF <= 7'h02; // C
                        3'h6:   r_opF <= 7'h02; // C
                        3'h7:   r_opF <= 7'h08; // V
                        3'h7:   r_opF <= 7'h08; // V
                        endcase
                        endcase
                end
                end
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
`else
 
        always @(posedge i_clk)
 
                if (op_ce)
 
                begin // Set the flag condition codes
 
                        case(dcdF[2:0])
 
                        3'h0:   opF <= 9'h100;  // Always
 
                        3'h1:   opF <= 9'h011;  // Z
 
                        3'h2:   opF <= 9'h010;  // NE
 
                        3'h3:   opF <= 9'h040;  // GE (!N)
 
                        3'h4:   opF <= 9'h050;  // GT (!N&!Z)
 
                        3'h5:   opF <= 9'h044;  // LT
 
                        3'h6:   opF <= 9'h022;  // C
 
                        3'h7:   opF <= 9'h088;  // V
 
                        endcase
 
                end
 
`endif
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
 
                begin
                        opvalid <= 1'b0;
                        opvalid <= 1'b0;
                else if (op_ce)
                        opvalid_alu <= 1'b0;
 
                        opvalid_mem <= 1'b0;
 
                end else if (op_ce)
 
                begin
                        // Do we have a valid instruction?
                        // Do we have a valid instruction?
                        //   The decoder may vote to stall one of its
                        //   The decoder may vote to stall one of its
                        //   instructions based upon something we currently
                        //   instructions based upon something we currently
                        //   have in our queue.  This instruction must then
                        //   have in our queue.  This instruction must then
                        //   move forward, and get a stall cycle inserted.
                        //   move forward, and get a stall cycle inserted.
                        //   Hence, the test on dcd_stalled here.  If we must
                        //   Hence, the test on dcd_stalled here.  If we must
                        //   wait until our operands are valid, then we aren't
                        //   wait until our operands are valid, then we aren't
                        //   valid yet until then.
                        //   valid yet until then.
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
                else if ((~op_stall)||(clear_pipeline))
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
 
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
 
                end else if ((~op_stall)||(clear_pipeline))
 
                begin
                        opvalid <= 1'b0;
                        opvalid <= 1'b0;
 
                        opvalid_alu <= 1'b0;
 
                        opvalid_mem <= 1'b0;
 
                end
 
 
        // Here's part of our debug interface.  When we recognize a break
        // Here's part of our debug interface.  When we recognize a break
        // instruction, we set the op_break flag.  That'll prevent this
        // instruction, we set the op_break flag.  That'll prevent this
        // instruction from entering the ALU, and cause an interrupt before
        // instruction from entering the ALU, and cause an interrupt before
        // this instruction.  Thus, returning to this code will cause the
        // this instruction.  Thus, returning to this code will cause the
        // break to repeat and continue upon return.  To get out of this
        // break to repeat and continue upon return.  To get out of this
        // condition, replace the break instruction with what it is supposed
        // condition, replace the break instruction with what it is supposed
        // to be, step through it, and then replace it back.  In this fashion,
        // to be, step through it, and then replace it back.  In this fashion,
        // a debugger can step through code.
        // a debugger can step through code.
 
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
 
        initial op_break = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)      op_break <= 1'b0;
                        op_break <= 1'b0;
                else if (op_ce) op_break <= (dcd_break);
                else if (op_ce)
                else if ((clear_pipeline)||(~opvalid))
                        op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
 
                else if ((~op_stall)||(clear_pipeline))
 
                        op_break <= 1'b0;
                        op_break <= 1'b0;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin
                begin
                        opn    <= dcdOp;        // Which ALU operation?
                        opn    <= dcdOp;        // Which ALU operation?
                        opM    <= dcdM;         // Is this a memory operation?
                        // opM  <= dcdM;        // Is this a memory operation?
                        // Will we write the flags/CC Register with our result?
                        // Will we write the flags/CC Register with our result?
                        opF_wr <= dcdF_wr;
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
                        // Will we be writing our results into a register?
                        // Will we be writing our results into a register?
                        opR_wr <= dcdA_wr;
                        opR_wr <= dcdA_wr;
                        // What register will these results be written into?
                        // What register will these results be written into?
                        opR    <= dcdA;
                        opR    <= dcdA;
 
                        opR_cc <= (dcdA_wr)&&(dcdA_cc);
                        // User level (1), vs supervisor (0)/interrupts disabled
                        // User level (1), vs supervisor (0)/interrupts disabled
                        op_gie <= dcd_gie;
                        op_gie <= dcd_gie;
 
 
                        // We're not done with these yet--we still need them
                        // We're not done with these yet--we still need them
                        // for the unclocked assign.  We need the unclocked
                        // for the unclocked assign.  We need the unclocked
                        // assign so that there's no wait state between an
                        // assign so that there's no wait state between an
                        // ALU or memory result and the next register that may
                        // ALU or memory result and the next register that may
                        // use that value.
                        // use that value.
                        opA_cc <= {dcdA[4], (dcdA[3:0] == `CPU_CC_REG) };
 
                        opA_rd <= dcdA_rd;
                        opA_rd <= dcdA_rd;
                        opB_cc <= {dcdB[4], (dcdB[3:0] == `CPU_CC_REG) };
 
                        opB_rd <= dcdB_rd;
                        opB_rd <= dcdB_rd;
                        op_pc  <= dcd_pc;
                        op_pc  <= dcd_pc;
                        //
                        //
                        op_wr_pc <= ((dcdA_wr)&&(dcdA[3:0] == `CPU_PC_REG));
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc));
                end
                end
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
 
 
        // This is tricky.  First, the PC and Flags registers aren't kept in
        // This is tricky.  First, the PC and Flags registers aren't kept in
        // register set but in special registers of their own.  So step one
        // register set but in special registers of their own.  So step one
Line 573... Line 585...
        // The alternative approach would be to define some sort of
        // The alternative approach would be to define some sort of
        // op_stall wire, which would stall any upstream stage.
        // op_stall wire, which would stall any upstream stage.
        // We'll create a flag here to start our coordination.  Once we
        // We'll create a flag here to start our coordination.  Once we
        // define this flag to something other than just plain zero, then
        // define this flag to something other than just plain zero, then
        // the stalls will already be in place.
        // the stalls will already be in place.
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&
`define DONT_STALL_ON_OPA
                                (((opvalid)&&(opR_wr)&&(opR == dcdA))
`ifdef  DONT_STALL_ON_OPA
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA))
        reg     opA_alu;
                                        ||((mem_valid)&&(mem_wreg == dcdA)));
        always @(posedge i_clk)
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)
                if (op_ce)
                                &&(((opvalid)&&(opR_wr)&&(opR == dcdB))
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd);
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))
        assign  opA = (opA_alu) ? alu_result : r_opA;
                                        ||((mem_valid)&&(mem_wreg == dcdB)));
`else
        assign  dcdF_stall = (dcdvalid)&&(((dcdF[3])
        assign  opA = r_opA;
                                        ||(dcdA[3:0]==`CPU_CC_REG)
`endif
                                        ||(dcdB[3:0]==`CPU_CC_REG))
 
                                &&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
 
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
 
        assign  opA = { r_opA[31:8], ((opA_cc[0]) ?
 
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
 
        assign  opB = { r_opB[31:8], ((opB_cc[0]) ?
 
                        ((opB_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
 
 
 
 
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
 
`define DONT_STALL_ON_OPB
 
`ifdef  DONT_STALL_ON_OPB
 
                // Skip the requirement on writing back opA
 
                // Stall on memory, since we'll always need to stall for a 
 
                // memory access anyway
 
                                ((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
 
`else
 
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))||
 
`endif
 
                                        ((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
 
`ifdef  DONT_STALL_ON_OPB
 
        reg     opB_alu;
 
        always @(posedge i_clk)
 
                if (op_ce)
 
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
 
        assign  opB = (opB_alu) ? alu_result : r_opB;
 
`else
 
        assign  opB = r_opB;
 
`endif
 
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
 
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
 
`ifdef  DONT_STALL_ON_OPB
 
                                        &&((opvalid_mem)||(dcdI != 0))
 
`endif
 
                                )||
 
                                ((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
 
        assign  dcdF_stall = (dcdvalid)&&(
 
                                (((~dcdF[3]) ||(dcdA_cc) ||(dcdB_cc))
 
                                        &&(opvalid)&&((opR_cc)||(opF_wr)))
 
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: Apply Instruction
        //      PIPELINE STAGE #4 :: Apply Instruction
        //
        //
        //
        //
        cpuops  doalu(i_clk, i_rst, alu_ce,
        cpuops  doalu(i_clk, i_rst, alu_ce,
                        (opvalid)&&(~opM), opn, opA, opB,
                        (opvalid_alu), opn, opA, opB,
                        alu_result, alu_flags, alu_valid);
                        alu_result, alu_flags, alu_valid);
 
 
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        initial alF_wr   = 1'b0;
        initial alF_wr   = 1'b0;
        initial alu_wr   = 1'b0;
        initial alu_wr   = 1'b0;
Line 628... Line 664...
                if ((alu_ce)||(mem_ce))
                if ((alu_ce)||(mem_ce))
                        alu_pc  <= op_pc;
                        alu_pc  <= op_pc;
        initial alu_pc_valid = 1'b0;
        initial alu_pc_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
                                        &&((~opM)
                                        &&((opvalid_alu)||(~mem_stalled));
                                                ||(~mem_stalled));
 
 
 
        memops  domem(i_clk, i_rst, mem_ce,
        memops  domem(i_clk, i_rst, mem_ce,
                                (opn[0]), opB, opA, opR,
                                (opn[0]), opB, opA, opR,
                                mem_busy, mem_valid, mem_wreg, mem_result,
                                mem_busy, mem_valid, mem_wreg, mem_result,
                        mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
                        mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
Line 670... Line 705...
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      Further, alu_wr includes (set_cond), so we don't need to
        //      check for that here either.
        //      check for that here either.
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
        // Which register shall be written?
        // Which register shall be written?
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
 
        // Are we writing to the CC register?
 
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
        // Are we writing to the PC?
        // Are we writing to the PC?
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
        // What value to write?
        // What value to write?
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 685... Line 722...
        //
        //
        // Write back to the condition codes/flags register ...
        // Write back to the condition codes/flags register ...
        // When shall we write to our flags register?  alF_wr already
        // When shall we write to our flags register?  alF_wr already
        // includes the set condition ...
        // includes the set condition ...
        assign  wr_flags_ce = (alF_wr)&&(alu_valid);
        assign  wr_flags_ce = (alF_wr)&&(alu_valid);
        assign  w_uflags = { 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_uflags = { trap, 1'b0, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
        assign  w_iflags = { break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
        assign  w_iflags = { trap, 1'b0, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
        // What value to write?
        // What value to write?
        always @(posedge i_clk)
        always @(posedge i_clk)
                // If explicitly writing the register itself
                // If explicitly writing the register itself
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
                        flags <= wr_reg_vl[3:0];
                        flags <= wr_reg_vl[3:0];
                // Otherwise if we're setting the flags from an ALU operation
                // Otherwise if we're setting the flags from an ALU operation
                else if ((wr_flags_ce)&&(alu_gie))
                else if ((wr_flags_ce)&&(alu_gie))
                        flags <= alu_flags;
                        flags <= alu_flags;
                else if ((i_halt)&&(i_dbg_we)
                else if ((i_halt)&&(i_dbg_we)
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
                        flags <= i_dbg_data[3:0];
                        flags <= i_dbg_data[3:0];
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        iflags <= wr_reg_vl[3:0];
                        iflags <= wr_reg_vl[3:0];
                else if ((wr_flags_ce)&&(~alu_gie))
                else if ((wr_flags_ce)&&(~alu_gie))
                        iflags <= alu_flags;
                        iflags <= alu_flags;
                else if ((i_halt)&&(i_dbg_we)
                else if ((i_halt)&&(i_dbg_we)
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
Line 727... Line 764...
        //      condition has taken place.
        //      condition has taken place.
        initial break_en = 1'b0;
        initial break_en = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_halt))
                if ((i_rst)||(i_halt))
                        break_en <= 1'b0;
                        break_en <= 1'b0;
                else if ((wr_reg_ce)&&(wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}))
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
        assign  o_break = (break_en)&&(op_break);
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy);
 
 
 
 
        // The sleep register.  Setting the sleep register causes the CPU to
        // The sleep register.  Setting the sleep register causes the CPU to
        // sleep until the next interrupt.  Setting the sleep register within
        // sleep until the next interrupt.  Setting the sleep register within
        // interrupt mode causes the processor to halt until a reset.  This is
        // interrupt mode causes the processor to halt until a reset.  This is
        // a panic/fault halt.
        // a panic/fault halt.  The trick is that you cannot be allowed to
 
        // set the sleep bit and switch to supervisor mode in the same 
 
        // instruction: users are not allowed to halt the CPU.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||((i_interrupt)&&(gie)))
                if ((i_rst)||((i_interrupt)&&(gie)))
                        sleep <= 1'b0;
                        sleep <= 1'b0;
                else if ((wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG))
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
 
                        // In supervisor mode, we have no protections.  The
 
                        // supervisor can set the sleep bit however he wants.
 
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
 
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
 
                        // In user mode, however, you can only set the sleep
 
                        // mode while remaining in user mode.  You can't switch
 
                        // to sleep mode *and* supervisor mode at the same
 
                        // time, lest you halt the CPU.
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
                else if ((i_halt)&&(i_dbg_we)
                else if ((i_halt)&&(i_dbg_we)
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(w_switch_to_interrupt))
                if ((i_rst)||(w_switch_to_interrupt))
                        step <= 1'b0;
                        step <= 1'b0;
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4:0] == {1'b1,`CPU_CC_REG}))
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
                        step <= wr_reg_vl[`CPU_STEP_BIT];
                        step <= wr_reg_vl[`CPU_STEP_BIT];
                else if ((i_halt)&&(i_dbg_we)
                else if ((i_halt)&&(i_dbg_we)
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
                        step <= i_dbg_data[`CPU_STEP_BIT];
                        step <= i_dbg_data[`CPU_STEP_BIT];
                else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
                else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
Line 764... Line 811...
                        (i_interrupt)
                        (i_interrupt)
                        // If we are stepping the CPU
                        // If we are stepping the CPU
                        ||((master_ce)&&(alu_pc_valid)&&(step))
                        ||((master_ce)&&(alu_pc_valid)&&(step))
                        // If we encounter a break instruction, if the break
                        // If we encounter a break instruction, if the break
                        //      enable isn't not set.
                        //      enable isn't not set.
                        ||((master_ce)&&(op_break))
                        ||((master_ce)&&(op_break)&&(~break_en))
                        // If we write to the CC register
                        // If we write to the CC register
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
                                &&(wr_reg_id[4])&&(wr_write_cc))
                        // Or if, in debug mode, we write to the CC register
                        // Or if, in debug mode, we write to the CC register
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
                        );
                        );
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
                        // Then if we write the CC register
                        // Then if we write the CC register
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
                                &&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
                                &&(~wr_reg_id[4])&&(wr_write_cc))
                        // Or if, in debug mode, we write the CC register
                        // Or if, in debug mode, we write the CC register
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
                        );
                        );
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 788... Line 835...
                else if (w_switch_to_interrupt)
                else if (w_switch_to_interrupt)
                        gie <= 1'b0;
                        gie <= 1'b0;
                else if (w_release_from_interrupt)
                else if (w_release_from_interrupt)
                        gie <= 1'b1;
                        gie <= 1'b1;
 
 
 
        initial trap = 1'b0;
 
        always @(posedge i_clk)
 
                if (i_rst)
 
                        trap <= 1'b0;
 
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
 
                                &&(wr_reg_id[4])&&(wr_write_cc))
 
                        trap <= 1'b1;
 
                else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
 
                                &&(~i_dbg_data[`CPU_GIE_BIT]))
 
                        trap <= i_dbg_data[`CPU_TRAP_BIT];
 
                else if (w_release_from_interrupt)
 
                        trap <= 1'b0;
 
 
        //
        //
        // Write backs to the PC register, and general increments of it
        // Write backs to the PC register, and general increments of it
        //      We support two: upc and ipc.  If the instruction is normal,
        //      We support two: upc and ipc.  If the instruction is normal,
        // we increment upc, if interrupt level we increment ipc.  If
        // we increment upc, if interrupt level we increment ipc.  If
        // the instruction writes the PC, we write whichever PC is appropriate.
        // the instruction writes the PC, we write whichever PC is appropriate.
Line 857... Line 917...
                begin
                begin
                        o_dbg_reg <= regset[i_dbg_reg];
                        o_dbg_reg <= regset[i_dbg_reg];
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                                o_dbg_reg <= { 25'h00, step, gie, sleep,
                                o_dbg_reg[9:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                        ((i_dbg_reg[4])?flags:iflags) };
 
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_cc <= { break_en, step, gie, sleep };
                o_dbg_cc <= { gie, sleep };
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy)
                o_dbg_stall <= (i_halt)&&(
 
                        (pf_cyc)||(mem_cyc)||(mem_busy)
                        ||((~opvalid)&&(~i_rst))
                        ||((~opvalid)&&(~i_rst))
                        ||((~dcdvalid)&&(~i_rst));
                        ||((~dcdvalid)&&(~i_rst)));
 
 
        //
        //
        //
        //
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // later evaluate how well we are doing.
        // later evaluate how well we are doing.

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.