| Line 268... |
Line 268... |
// Calculate stall conditions
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// Calculate stall conditions
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//
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//
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// PIPELINE STAGE #2 :: Instruction Decode
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// PIPELINE STAGE #2 :: Instruction Decode
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// Calculate stall conditions
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// Calculate stall conditions
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assign dcd_ce = (pf_valid)&&(~dcd_stalled);
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assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
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assign dcd_stalled = (dcdvalid)&&(
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assign dcd_stalled = (dcdvalid)&&(
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(op_stall)
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(op_stall)
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||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
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||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
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||((opvalid)&&((op_wr_pc)||(opR_cc))));
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||((opvalid)&&((op_wr_pc)||(opR_cc))));
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//
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//
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| Line 762... |
Line 762... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_halt))
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if ((i_rst)||(i_halt))
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break_en <= 1'b0;
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break_en <= 1'b0;
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else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
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else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
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break_en <= wr_reg_vl[`CPU_BREAK_BIT];
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break_en <= wr_reg_vl[`CPU_BREAK_BIT];
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else if ((i_halt)&&(i_dbg_we)
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&&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
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break_en <= i_dbg_data[`CPU_BREAK_BIT];
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assign o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy);
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assign o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy);
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// The sleep register. Setting the sleep register causes the CPU to
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// The sleep register. Setting the sleep register causes the CPU to
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// sleep until the next interrupt. Setting the sleep register within
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// sleep until the next interrupt. Setting the sleep register within
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| Line 884... |
Line 887... |
else if (w_release_from_interrupt)
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else if (w_release_from_interrupt)
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pf_pc <= upc;
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pf_pc <= upc;
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else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
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else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
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pf_pc <= wr_reg_vl;
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pf_pc <= wr_reg_vl;
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else if ((i_halt)&&(i_dbg_we)
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else if ((i_halt)&&(i_dbg_we)
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&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
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&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
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pf_pc <= i_dbg_data;
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pf_pc <= i_dbg_data;
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else if (dcd_ce)
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else if (dcd_ce)
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pf_pc <= pf_pc + 1;
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pf_pc <= pf_pc + 1;
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initial new_pc = 1'b1;
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initial new_pc = 1'b1;
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| Line 900... |
Line 903... |
else if (w_release_from_interrupt)
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else if (w_release_from_interrupt)
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new_pc <= 1'b1;
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new_pc <= 1'b1;
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else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
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else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
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new_pc <= 1'b1;
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new_pc <= 1'b1;
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else if ((i_halt)&&(i_dbg_we)
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else if ((i_halt)&&(i_dbg_we)
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&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
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&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
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new_pc <= 1'b1;
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new_pc <= 1'b1;
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else
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else
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new_pc <= 1'b0;
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new_pc <= 1'b0;
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//
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//
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