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//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     This is the top level module holding the core of the Zip CPU
// Purpose:     This is the top level module holding the core of the Zip CPU
//              together.  The Zip CPU is designed to be as simple as possible.
//              together.  The Zip CPU is designed to be as simple as possible.
//              The instruction set is about as RISC as you can get, there are
//      (actual implementation aside ...)  The instruction set is about as
//              only 16 instruction types supported (of which one isn't yet
//      RISC as you can get, there are only 16 instruction types supported.
//              supported ...)  Please see the accompanying iset.html file
//      Please see the accompanying spec.pdf file for a description of these
//              for a description of these instructions.
//      instructions.
//
//
//              All instructions are 32-bits wide.  All bus accesses, both
//      All instructions are 32-bits wide.  All bus accesses, both address and
//              address and data, are 32-bits over a wishbone bus.
//      data, are 32-bits over a wishbone bus.
//
//
//      The Zip CPU is fully pipelined with the following pipeline stages:
//      The Zip CPU is fully pipelined with the following pipeline stages:
//
//
//              1. Prefetch, returns the instruction from memory.  On the
//              1. Prefetch, returns the instruction from memory. 
//              Basys board that I'm working on, one instruction may be
 
//              issued every 20 clocks or so, unless and until I implement a
 
//              cache or local memory.
 
//
//
//              2. Instruction Decode
//              2. Instruction Decode
//
//
//              3. Read Operands
//              3. Read Operands
//
//
//              4. Apply Instruction
//              4. Apply Instruction
//
//
//              4. Write-back Results
//              4. Write-back Results
//
//
//      A lot of difficult work has been placed into the pipeline stall
//      Further information about the inner workings of this CPU may be
//      handling.  My original proposal was not to allow pipeline stalls at all.
//      found in the spec.pdf file.  (The documentation within this file
//      The idea would be that the CPU would just run every clock and whatever
//      had become out of date and out of sync with the spec.pdf, so look
//      stalled answer took place would just get fixed a clock or two later,
//      to the spec.pdf for accurate and up to date information.)
//      meaning that the compiler could just schedule everything out.
 
//      This idea died at the memory interface, which can take a variable
 
//      amount of time to read or write any value, thus the whole CPU needed
 
//      to stall on a stalled memory access.
 
//
 
//      My next idea was to just let things complete.  I.e., once an instrution
 
//      starts, it continues to completion no matter what and we go on.  This
 
//      failed at writing the PC.  If the PC gets written in something such as
 
//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
 
//      later, if whether or not something happens in those clocks depends
 
//      upon the instruction fetch filling the pipeline, then the CPU has a
 
//      non-deterministic behavior.
 
//
 
//      This leads to two possibilities: either *everything* stalls upon a 
 
//      stall condition, or partial results need to be destroyed before
 
//      they are written.  This is made more difficult by the fact that
 
//      once a command is written to the memory unit, whether it be a
 
//      read or a write, there is no undoing it--since peripherals on the
 
//      bus may act upon the answer with whatever side effects they might
 
//      have.  (For example, writing a '1' to the interrupt register will
 
//      clear certain interrupts ...)  Further, since the memory ops depend
 
//      upon conditions, the we'll need to wait for the condition codes to
 
//      be available before executing a memory op.  Thus, memory ops can 
 
//      proceed without stalling whenever either the previous instruction
 
//      doesn't write the flags register, or when the memory instruction doesn't
 
//      depend upon the flags register.
 
//
 
//      The other possibility is that we leave independent instruction
 
//      execution behind, so that the pipeline is always full and stalls,
 
//      or moves forward, together on every clock.
 
//
 
//      For now, we pick the first approach: independent instruction execution.
 
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
 
//      in their pipeline.  This leaves another problem: what happens on a
 
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
 
//      one (or is it five?) that will need to be 'cancelled'.  So here's
 
//      the plan: Anything can be cancelled before the ALU/MEM stage,
 
//      since memory ops cannot be canceled after being issued.  Thus, the
 
//      ALU/MEM stage must stall if any prior instruction is going to write
 
//      the PC register (i.e. JMP).
 
//
 
//      Further, let's define a "STALL" as a reason to not execute a stage
 
//      due to some condition at or beyond the stage, and let's define
 
//      a VALID flag to mean that this stage has completed.  Thus, the clock
 
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
 
//      The ALU/MEM stages will also depend upon a master clock enable
 
//      (~SLEEP) condition as well.
 
//
 
//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
Line 126... Line 75...
`define CPU_BREAK_BIT   7
`define CPU_BREAK_BIT   7
`define CPU_STEP_BIT    6
`define CPU_STEP_BIT    6
`define CPU_GIE_BIT     5
`define CPU_GIE_BIT     5
`define CPU_SLEEP_BIT   4
`define CPU_SLEEP_BIT   4
// Compile time defines
// Compile time defines
// (Currently unused)
//
// `define      OPT_SINGLE_FETCH
`include "cpudefs.v"
// (Best path--define these!)
//
`define OPT_CONDITIONAL_FLAGS
 
`define OPT_ILLEGAL_INSTRUCTION
 
`ifndef OPT_SINGLE_FETCH
 
        // The following are pipeline optimization options.
 
        // They make no sense in a single instruction fetch mode.
 
`define OPT_PRECLEAR_BUS
 
`define OPT_EARLY_BRANCHING
 
`define OPT_PIPELINED_BUS_ACCESS
 
`endif
 
module  zipcpu(i_clk, i_rst, i_interrupt,
module  zipcpu(i_clk, i_rst, i_interrupt,
                // Debug interface
                // Debug interface
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
                        o_break,
                        o_break,
Line 150... Line 90...
                        o_wb_lcl_cyc, o_wb_lcl_stb,
                        o_wb_lcl_cyc, o_wb_lcl_stb,
                        o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                        i_wb_err,
                        i_wb_err,
                // Accounting/CPU usage interface
                // Accounting/CPU usage interface
                o_op_stall, o_pf_stall, o_i_count);
                o_op_stall, o_pf_stall, o_i_count,
 
                //
 
                o_debug);
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
                        LGICACHE=6, AW=ADDRESS_WIDTH;
                        LGICACHE=6, AW=ADDRESS_WIDTH;
 
`ifdef  OPT_MULTIPLY
 
        parameter       IMPLEMENT_MPY = 1;
 
`else
 
        parameter       IMPLEMENT_MPY = 0;
 
`endif
        input                   i_clk, i_rst, i_interrupt;
        input                   i_clk, i_rst, i_interrupt;
        // Debug interface -- inputs
        // Debug interface -- inputs
        input                   i_halt, i_clear_pf_cache;
        input                   i_halt, i_clear_pf_cache;
        input           [4:0]    i_dbg_reg;
        input           [4:0]    i_dbg_reg;
        input                   i_dbg_we;
        input                   i_dbg_we;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
        // Debug interface -- outputs
        // Debug interface -- outputs
        output  reg             o_dbg_stall;
        output  reg             o_dbg_stall;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [31:0]   o_dbg_reg;
        output  reg     [1:0]    o_dbg_cc;
        output  reg     [3:0]    o_dbg_cc;
        output  wire            o_break;
        output  wire            o_break;
        // Wishbone interface -- outputs
        // Wishbone interface -- outputs
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [(AW-1):0]       o_wb_addr;
Line 177... Line 124...
        input                   i_wb_err;
        input                   i_wb_err;
        // Accounting outputs ... to help us count stalls and usage
        // Accounting outputs ... to help us count stalls and usage
        output  wire            o_op_stall;
        output  wire            o_op_stall;
        output  wire            o_pf_stall;
        output  wire            o_pf_stall;
        output  wire            o_i_count;
        output  wire            o_i_count;
 
        //
 
        output  reg     [31:0]   o_debug;
 
 
 
 
        // Registers
        // Registers
 
        //
 
        //      The distributed RAM style comment is necessary on the
 
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
 
        // set and in the process ruining everything else.  It basically
 
        // optimizes logic away, to where it no longer works.  The logic
 
        // as described herein will work, this just makes sure XST implements
 
        // that logic.
 
        //
 
        (* ram_style = "distributed" *)
        reg     [31:0]   regset [0:31];
        reg     [31:0]   regset [0:31];
 
 
        // Condition codes
        // Condition codes
        reg     [3:0]    flags, iflags;  // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
 
        reg     [3:0]    flags, iflags;
        wire    [10:0]   w_uflags, w_iflags;
        wire    [10:0]   w_uflags, w_iflags;
        reg             trap, break_en, step, gie, sleep;
        reg             trap, break_en, step, gie, sleep;
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg             ill_err;
        reg             ill_err;
`else
`else
Line 230... Line 189...
        reg     [3:0]    dcdF;
        reg     [3:0]    dcdF;
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
        reg     [(AW-1):0]       dcd_pc;
        reg     [(AW-1):0]       dcd_pc;
        reg     [23:0]   r_dcdI;
        reg     [23:0]   r_dcdI;
 
`ifdef  OPT_SINGLE_CYCLE
        reg             dcd_zI; // true if dcdI == 0
        reg             dcd_zI; // true if dcdI == 0
 
`endif
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
 
 
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
        reg     dcd_clear_bus;
        reg     dcd_clear_bus;
`endif
`endif
Line 263... Line 224...
        reg     [4:0]    opR;
        reg     [4:0]    opR;
        reg     [31:0]   r_opA, r_opB;
        reg     [31:0]   r_opA, r_opB;
        reg     [(AW-1):0]       op_pc;
        reg     [(AW-1):0]       op_pc;
        wire    [31:0]   w_opA, w_opB;
        wire    [31:0]   w_opA, w_opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
        reg             opR_wr, opR_cc, opF_wr, op_gie,
        reg             opR_wr, opR_cc, opF_wr, op_gie;
                        opA_rd, opB_rd;
 
        wire    [10:0]   opFl;
        wire    [10:0]   opFl;
        reg     [6:0]    r_opF;
        reg     [5:0]    r_opF;
        wire    [8:0]    opF;
        wire    [7:0]    opF;
 
        reg     [2:0]    opF_cp;
        wire            op_ce;
        wire            op_ce;
 
        // Some pipeline control wires
 
`ifdef  OPT_SINGLE_CYCLE
 
        reg     opA_alu, opA_mem;
 
        reg     opB_alu, opB_mem;
 
`endif
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
        reg     op_clear_bus;
        reg     op_clear_bus;
`endif
`endif
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
        reg     op_illegal;
        reg     op_illegal;
Line 291... Line 257...
        wire    [31:0]   alu_result;
        wire    [31:0]   alu_result;
        wire    [3:0]    alu_flags;
        wire    [3:0]    alu_flags;
        wire            alu_valid;
        wire            alu_valid;
        wire            set_cond;
        wire            set_cond;
        reg             alu_wr, alF_wr, alu_gie;
        reg             alu_wr, alF_wr, alu_gie;
`ifdef  OPT_ILLEGAL_INSTRUCTION
        wire            alu_illegal_op;
        reg             alu_illegal;
 
`else
 
        wire            alu_illegal;
        wire            alu_illegal;
`endif
 
 
 
 
 
 
 
        wire    mem_ce, mem_stalled;
        wire    mem_ce, mem_stalled;
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
Line 349... Line 312...
                                        ||((opvalid_mem)&&(op_wr_pc))
                                        ||((opvalid_mem)&&(op_wr_pc))
                                        ||((opvalid_mem)&&(opR_cc)));
                                        ||((opvalid_mem)&&(opR_cc)));
        //
        //
        //      PIPELINE STAGE #3 :: Read Operands
        //      PIPELINE STAGE #3 :: Read Operands
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign  op_stall = ((mem_stalled)&&(opvalid_mem))
        assign  op_stall = ((opvalid)&&(~master_ce))||(
                                ||((alu_stall)&&(opvalid_alu));
                        // Stall if going into the ALU and the ALU is stalled
 
                        //      i.e. if the memory is busy, or we are single
 
                        //      stepping
 
                        ((opvalid_alu)&&(alu_stall))
 
                        //
 
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
 
                        // Stall if we are going into memory with an operation
 
                        //      that cannot be pipelined, and the memory is
 
                        //      already busy
 
                        ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
 
                        //
 
                        // Stall if we are going into memory with a pipeable
 
                        //      operation, but the memory unit declares it is
 
                        //      not going to accept any more pipeline operations
 
                        ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
 
 
        //
        //
        //      PIPELINE STAGE #4 :: ALU / Memory
        //      PIPELINE STAGE #4 :: ALU / Memory
        //              Calculate stall conditions
        //              Calculate stall conditions
        //
        //
        // 1. Basic stall is if the previous stage is valid and the next is
        // 1. Basic stall is if the previous stage is valid and the next is
        //      busy.  
        //      busy.  
        // 2. Also stall if the prior stage is valid and the master clock enable
        // 2. Also stall if the prior stage is valid and the master clock enable
        //      is de-selected
        //      is de-selected
        // 3. Next case: Stall if we want to start a memory operation and the
        // 3. Stall if someone on the other end is writing the CC register,
        //      prior operation will write either the PC or CC registers.
        //      since we don't know if it'll put us to sleep or not.
        // 4. Last case: Stall if we would otherwise move a break instruction
        // 4. Last case: Stall if we would otherwise move a break instruction
        //      through the ALU.  Break instructions are not allowed through
        //      through the ALU.  Break instructions are not allowed through
        //      the ALU.
        //      the ALU.
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
                        ||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                        // Old case #3--this isn't an ALU stall though ...
                                &&((wr_write_pc)||(wr_write_cc))) // Case 3
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
                        ||((opvalid)&&(op_break)); // Case 4
                                &&(wr_write_cc)) // Case 3
 
                        ||((opvalid_alu)&&(op_break)); // Case 3
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
        //
        //
`ifdef  OPT_PIPELINED_BUS_ACCESS
`ifdef  OPT_PIPELINED_BUS_ACCESS
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
                        &&(set_cond)&&(~mem_stalled);
                        &&(set_cond)&&(~mem_stalled);
Line 441... Line 419...
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
                        dcdvalid <= 1'b0;
                        dcdvalid <= 1'b0;
 
 
`ifdef  OPT_EARLY_BRANCHING
`ifdef  OPT_EARLY_BRANCHING
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(~sleep))
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
                begin
                begin
                        dcd_early_branch <= 1'b0;
                        dcd_early_branch <= 1'b0;
                        // First case, a move to PC instruction
                        // First case, a move to PC instruction
                        if ((instruction[31:28] == 4'h2)
                        if ((instruction[31:28] == 4'h2)
                                &&((instruction_gie)
                                &&((instruction_gie)
Line 474... Line 452...
                end else
                end else
                begin
                begin
                        if (dcd_ce) dcd_early_branch <= 1'b0;
                        if (dcd_ce) dcd_early_branch <= 1'b0;
                        dcd_early_branch_stb <= 1'b0;
                        dcd_early_branch_stb <= 1'b0;
                end
                end
 
        generate
 
        if (AW == 24)
 
        begin
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dcd_ce)
                if (dcd_ce)
                begin
                begin
                        if (instruction[31]) // Add
                        if (instruction[31]) // Add
                                dcd_branch_pc <= instruction_pc+{ {(AW-20){instruction[19]}}, instruction[19:0] } + {{(AW-1){1'b0}},1'b1};
                        begin
                        else if (~instruction[28]) // 4'h2 = MOV
                                dcd_branch_pc <= instruction_pc
 
                                                + { {(AW-20){instruction[19]}}, instruction[19:0] }
 
                                                + {{(AW-1){1'b0}},1'b1};
 
                        end else if (~instruction[28]) // 4'h2 = MOV
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
                        else // if (instruction[28]) // 4'h3 = LDI
                        else // if (instruction[28]) // 4'h3 = LDI
 
                                dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
 
                end
 
        end else begin
 
                always @(posedge i_clk)
 
                if (dcd_ce)
 
                begin
 
                        if (instruction[31]) // Add
 
                        begin
 
                                dcd_branch_pc <= instruction_pc
 
                                                        + { {(AW-20){instruction[19]}}, instruction[19:0] }
 
                                                        + {{(AW-1){1'b0}},1'b1};
 
                        end else if (~instruction[28]) // 4'h2 = MOV
 
                        begin
 
                                        dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
 
                        end else // if (instruction[28]) // 4'h3 = LDI
 
                        begin
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
                end
                end
 
                end
 
        end endgenerate
`else   //      OPT_EARLY_BRANCHING
`else   //      OPT_EARLY_BRANCHING
        assign  dcd_early_branch_stb = 1'b0;
        assign  dcd_early_branch_stb = 1'b0;
        assign  dcd_early_branch     = 1'b0;
        assign  dcd_early_branch     = 1'b0;
        assign  dcd_branch_pc        = {(AW){1'b0}};
        assign  dcd_branch_pc        = {(AW){1'b0}};
`endif  //      OPT_EARLY_BRANCHING
`endif  //      OPT_EARLY_BRANCHING
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dcd_ce)
                if (dcd_ce)
                begin
                begin
                        dcd_pc <= instruction_pc+1;
                        dcd_pc <= instruction_pc
 
                                +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
 
 
                        // Record what operation we are doing
                        // Record what operation we are doing
                        dcdOp <= instruction[31:28];
                        dcdOp <= instruction[31:28];
 
 
                        // Default values
                        // Default values
Line 533... Line 536...
                                end
                                end
                                dcdA_wr <= 1'b1;
                                dcdA_wr <= 1'b1;
                                dcdA_rd <= 1'b0;
                                dcdA_rd <= 1'b0;
                                dcdB_rd <= 1'b1;
                                dcdB_rd <= 1'b1;
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                dcd_zI <= (instruction[14:0] == 0);
                                dcd_zI <= (instruction[14:0] == 0);
 
`endif
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                end
                                end
                        4'h3: begin // Load immediate
                        4'h3: begin // Load immediate
                                dcdA_wr <= 1'b1;
                                dcdA_wr <= 1'b1;
                                dcdA_rd <= 1'b0;
                                dcdA_rd <= 1'b0;
                                dcdB_rd <= 1'b0;
                                dcdB_rd <= 1'b0;
                                r_dcdI <= { instruction[23:0] };
                                r_dcdI <= { instruction[23:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                dcd_zI <= (instruction[23:0] == 0);
                                dcd_zI <= (instruction[23:0] == 0);
 
`endif
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF    <= 4'h8; // This is unconditional
                                dcdF    <= 4'h8; // This is unconditional
                                dcdOp <= 4'h2;
                                dcdOp <= 4'h2;
                                end
                                end
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
Line 557... Line 564...
`else
`else
                                // Don't write flags except for multiplies
                                // Don't write flags except for multiplies
                                dcdF_wr <= (instruction[27:25] != 3'h7);
                                dcdF_wr <= (instruction[27:25] != 3'h7);
`endif
`endif
                                r_dcdI <= { 8'h00, instruction[15:0] };
                                r_dcdI <= { 8'h00, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                dcd_zI <= (instruction[15:0] == 0);
                                dcd_zI <= (instruction[15:0] == 0);
 
`endif
                                if (instruction[27:24] == 4'he)
                                if (instruction[27:24] == 4'he)
                                begin
                                begin
                                        // NOOP instruction
                                        // NOOP instruction
                                        dcdA_wr <= 1'b0;
                                        dcdA_wr <= 1'b0;
                                        dcdA_rd <= 1'b0;
                                        dcdA_rd <= 1'b0;
Line 582... Line 591...
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
                                        dcdOp <= { 3'h3, instruction[20] };
                                        dcdOp <= { 3'h3, instruction[20] };
                                end else begin
                                end else begin
                                        // Actual multiply instruction
                                        // Actual multiply instruction
                                        r_dcdI <= { 8'h00, instruction[15:0] };
                                        r_dcdI <= { 8'h00, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[15:0] == 0);
                                        dcd_zI <= (instruction[15:0] == 0);
 
`endif
                                        dcdA_rd <= 1'b1;
                                        dcdA_rd <= 1'b1;
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
                                end end
                                end end
                        4'b011?: begin // Load/Store
                        4'b011?: begin // LOD/STO or Load/Store
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdF_wr <= 1'b0; // Don't write flags
                                dcdA_wr <= (~instruction[28]); // Write on loads
                                dcdA_wr <= (~instruction[28]); // Write on loads
                                dcdA_rd <= (instruction[28]); // Read on stores
                                dcdA_rd <= (instruction[28]); // Read on stores
                                dcdB_rd <= instruction[20];
                                dcdB_rd <= instruction[20];
                                if (instruction[20])
                                if (instruction[20])
                                begin
                                begin
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[15:0] == 0);
                                        dcd_zI <= (instruction[15:0] == 0);
 
`endif
                                end else begin
                                end else begin
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[19:0] == 0);
                                        dcd_zI <= (instruction[19:0] == 0);
 
`endif
                                end
                                end
                                dcdM <= 1'b1; // Memory operation
                                dcdM <= 1'b1; // Memory operation
`ifdef  OPT_PRECLEAR_BUS
`ifdef  OPT_PRECLEAR_BUS
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
`endif
`endif
Line 612... Line 627...
                                dcdA_rd <= 1'b1;
                                dcdA_rd <= 1'b1;
                                dcdB_rd <= instruction[20];
                                dcdB_rd <= instruction[20];
                                if (instruction[20])
                                if (instruction[20])
                                begin
                                begin
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[15:0] == 0);
                                        dcd_zI <= (instruction[15:0] == 0);
 
`endif
                                end else begin
                                end else begin
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
 
`ifdef  OPT_SINGLE_CYCLE
                                        dcd_zI <= (instruction[19:0] == 0);
                                        dcd_zI <= (instruction[19:0] == 0);
 
`endif
                                end end
                                end end
                        endcase
                        endcase
 
 
 
 
                        dcd_gie <= instruction_gie;
                        dcd_gie <= instruction_gie;
Line 645... Line 664...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
                                &&(dcdB == op_B) // Same address register
                                &&(dcdB == op_B) // Same address register
 
                                &&(dcdF[2:0] == opF_cp) // Same condition
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        r_opI <= r_dcdI;
                        r_opI <= r_dcdI;
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 661... Line 681...
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
        //
        //
        //
        //
        assign  w_opA = regset[dcdA];
        assign  w_opA = regset[dcdA];
        assign  w_opB = regset[dcdB];
        assign  w_opB = regset[dcdB];
 
 
 
        wire    [31:0]   w_pcA_v;
 
        generate
 
        if (AW < 32)
 
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
 
        else
 
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
 
        endgenerate
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                begin
                begin
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_reg_vl;
                        else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
 
                                r_opA <= { {(32-AW){1'b0}}, dcd_pc };
 
                        else if (dcdA_pc)
                        else if (dcdA_pc)
                                r_opA <= { {(32-AW){1'b0}}, upc };
                                r_opA <= w_pcA_v;
                        else if (dcdA_cc)
                        else if (dcdA_cc)
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
                        else
                        else
                                r_opA <= w_opA;
                                r_opA <= w_opA;
 
`ifdef  OPT_SINGLE_CYCLE
                end else if (opvalid)
                end else if (opvalid)
                begin // We were going to pick these up when they became valid,
                begin // We were going to pick these up when they became valid,
                        // but for some reason we're stuck here as they became
                        // but for some reason we're stuck here as they became
                        // valid.  Pick them up now anyway
                        // valid.  Pick them up now anyway
                        if ((opA_alu)||((opA_mem)&&(mem_valid)))
                        if (((opA_alu)&&(alu_valid)&&(alu_wr))||((opA_mem)&&(mem_valid)))
                                r_opA <= wr_reg_vl;
                                r_opA <= wr_reg_vl;
 
`endif
                end
                end
        wire    [31:0]   dcdI, w_opBnI;
 
 
        wire    [31:0]   dcdI, w_opBnI, w_pcB_v;
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
 
        generate
 
        if (AW < 32)
 
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
 
        else
 
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
 
        endgenerate
 
 
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
                        : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
                        : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
                        : (((dcdB_pc)&&(dcdB[4] == dcd_gie)) ? {{(32-AW){1'b0}},dcd_pc }
                : ((dcdB_pc) ? w_pcB_v
                        : ((dcdB_pc) ? {{(32-AW){1'b0}},upc}
 
                        : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
                        : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
                        : regset[dcdB]))));
                : w_opB)));
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce) // &&(dcdvalid))
                if (op_ce) // &&(dcdvalid))
                        r_opB <= w_opBnI + dcdI;
                        r_opB <= w_opBnI + dcdI;
                else if ((opvalid)&&((opB_alu)||((opB_mem)&&(mem_valid))))
`ifdef  OPT_SINGLE_CYCLE
 
                else if ((opvalid)&&(
 
                                ((opB_alu)&&(alu_valid)&&(alu_wr))
 
                                ||((opB_mem)&&(mem_valid))))
                        r_opB <= wr_reg_vl;
                        r_opB <= wr_reg_vl;
 
`endif
 
 
        // The logic here has become more complex than it should be, no thanks
        // The logic here has become more complex than it should be, no thanks
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
        // be two sets of four bits: the top bits specify what bits matter, the
        // be two sets of four bits: the top bits specify what bits matter, the
        // bottom specify what those top bits must equal.  However, two of
        // bottom specify what those top bits must equal.  However, two of
Line 708... Line 748...
        // opF.
        // opF.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
                        case(dcdF[2:0])
                        case(dcdF[2:0])
                        3'h0:   r_opF <= 7'h80; // Always
                        3'h0:   r_opF <= 6'h00; // Always
                        3'h1:   r_opF <= 7'h11; // Z
                        3'h1:   r_opF <= 6'h11; // Z
                        3'h2:   r_opF <= 7'h10; // NE
                        3'h2:   r_opF <= 6'h10; // NE
                        3'h3:   r_opF <= 7'h20; // GE (!N)
                        3'h3:   r_opF <= 6'h20; // GE (!N)
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
                        3'h5:   r_opF <= 7'h24; // LT
                        3'h5:   r_opF <= 6'h24; // LT
                        3'h6:   r_opF <= 7'h02; // C
                        3'h6:   r_opF <= 6'h02; // C
                        3'h7:   r_opF <= 7'h08; // V
                        3'h7:   r_opF <= 6'h08; // V
                        endcase
                        endcase
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
 
        always @(posedge i_clk)
 
                if (op_ce)
 
                        opF_cp[2:0] <= dcdF[2:0];
 
 
        initial opvalid     = 1'b0;
        initial opvalid     = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_mem = 1'b0;
        initial opvalid_mem = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 796... Line 839...
                        opR    <= dcdA;
                        opR    <= dcdA;
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
                        // User level (1), vs supervisor (0)/interrupts disabled
                        // User level (1), vs supervisor (0)/interrupts disabled
                        op_gie <= dcd_gie;
                        op_gie <= dcd_gie;
 
 
                        // We're not done with these yet--we still need them
 
                        // for the unclocked assign.  We need the unclocked
 
                        // assign so that there's no wait state between an
 
                        // ALU or memory result and the next register that may
 
                        // use that value.
 
                        opA_rd <= dcdA_rd;
 
                        opB_rd <= dcdB_rd;
 
                        //
                        //
`ifdef  OPT_EARLY_BRANCHING
`ifdef  OPT_EARLY_BRANCHING
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
`else
`else
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
Line 830... Line 866...
        // The alternative approach would be to define some sort of
        // The alternative approach would be to define some sort of
        // op_stall wire, which would stall any upstream stage.
        // op_stall wire, which would stall any upstream stage.
        // We'll create a flag here to start our coordination.  Once we
        // We'll create a flag here to start our coordination.  Once we
        // define this flag to something other than just plain zero, then
        // define this flag to something other than just plain zero, then
        // the stalls will already be in place.
        // the stalls will already be in place.
        reg     opA_alu, opA_mem;
`ifdef  OPT_SINGLE_CYCLE
 
        initial opA_alu = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
                        opA_alu <= 1'b0;
                        opA_alu <= 1'b0;
 
        initial opA_mem = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd))
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd)&&(~opn[0]))
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
                        opA_mem <= 1'b0;
                        opA_mem <= 1'b0;
 
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (mem_ce)
                if (mem_ce)
                        mem_last_reg <= opR;
                        mem_last_reg <= opR;
        assign  opA = (opA_alu) ? alu_result
`ifdef  OPT_SINGLE_CYCLE
 
        assign  opA = ((opA_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
                        : ( ((opA_mem)&&(mem_valid))?mem_result
                        : ( ((opA_mem)&&(mem_valid))?mem_result
                        : r_opA );
                        : r_opA );
 
`else
 
        assign  opA = r_opA;
 
`endif
 
 
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
 
`ifdef  OPT_SINGLE_CYCLE
                // Skip the requirement on writing back opA
                // Skip the requirement on writing back opA
                // Stall on memory, since we'll always need to stall for a 
                // Stall on memory, since we'll always need to stall for a 
                // memory access anyway
                // memory access anyway
                                // ((opvalid_mem)&&(opR_wr)&&(opR == dcdA))
 
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
                // Place stalls for this latter case into the ops stage
`else
                //              ||((mem_busy)&&(~mem_we));
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))
 
                                ||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
 
                                ||((mem_rdbusy)&&(mem_last_reg == dcdA))
 
                                );
 
`endif
 
 
        reg     opB_alu, opB_mem;
`ifdef  OPT_SINGLE_CYCLE
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (op_ce)
                if (op_ce)
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
                                ((opvalid_mem)&&(opR == dcdB))
                                ((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
                                        &&(mem_last_reg == dcdB)));
                                        &&(mem_last_reg == dcdB)));
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
                        opB_mem <= 1'b0;
                        opB_mem <= 1'b0;
        assign  opB = (opB_alu) ? alu_result
        assign  opB = ((opB_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
                        : ( ((opB_mem)&&(mem_valid))?mem_result
                        : ( ((opB_mem)&&(mem_valid))?mem_result
                        : r_opB );
                        : r_opB );
 
`else
 
        assign  opB = r_opB;
 
`endif
 
 
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
 
`ifdef  OPT_SINGLE_CYCLE
                                // Stall on memory ops writing to my register
                                // Stall on memory ops writing to my register
                                //      (i.e. loads), or on any write to my
                                //      (i.e. loads), or on any write to my
                                //      register if I have an immediate offset
                                //      register if I have an immediate offset
                                // Note the exception for writing to the PC:
                                // Note the exception for writing to the PC:
                                //      if I write to the PC, the whole next
                                //      if I write to the PC, the whole next
Line 895... Line 947...
                                // opB.
                                // opB.
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
                                // Stall on any ongoing memory operation that
                                // Stall on any ongoing memory operation that
                                // will write to opB
                                // will write to opB
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
 
`else
 
                                ((opvalid)&&(opR_wr)&&(opR == dcdB))
 
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
 
                                ||((mem_rdbusy)&&(mem_last_reg == dcdB))
 
                                );
 
`endif
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
                                        &&(opvalid)&&(opR_cc);
                                        &&(opvalid)&&(opR_cc);
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: Apply Instruction
        //      PIPELINE STAGE #4 :: Apply Instruction
        //
        //
        //
        //
        cpuops  doalu(i_clk, i_rst, alu_ce,
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
                        (opvalid_alu), opn, opA, opB,
                        (opvalid_alu), opn, opA, opB,
                        alu_result, alu_flags, alu_valid);
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
 
 
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
        initial alF_wr   = 1'b0;
        initial alF_wr   = 1'b0;
        initial alu_wr   = 1'b0;
        initial alu_wr   = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 932... Line 990...
                        alu_gie  <= op_gie;
                        alu_gie  <= op_gie;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((alu_ce)||(mem_ce))
                if ((alu_ce)||(mem_ce))
                        alu_pc  <= op_pc;
                        alu_pc  <= op_pc;
`ifdef  OPT_ILLEGAL_INSTRUCTION
`ifdef  OPT_ILLEGAL_INSTRUCTION
 
        reg     r_alu_illegal;
 
        initial r_alu_illegal = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((alu_ce)||(mem_ce))
                if ((alu_ce)||(mem_ce))
                        alu_illegal <= op_illegal;
                        r_alu_illegal <= op_illegal;
 
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
`endif
`endif
 
 
        initial alu_pc_valid = 1'b0;
        initial alu_pc_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
Line 1235... Line 1296...
                        pf_pc <= wr_reg_vl[(AW-1):0];
                        pf_pc <= wr_reg_vl[(AW-1):0];
                else if ((i_halt)&&(i_dbg_we)
                else if ((i_halt)&&(i_dbg_we)
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
                        pf_pc <= i_dbg_data[(AW-1):0];
                        pf_pc <= i_dbg_data[(AW-1):0];
                else if (dcd_ce)
                else if (dcd_ce)
                        pf_pc <= pf_pc + 1;
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
 
 
        initial new_pc = 1'b1;
        initial new_pc = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_pf_cache))
                if ((i_rst)||(i_clear_pf_cache))
                        new_pc <= 1'b1;
                        new_pc <= 1'b1;
Line 1255... Line 1316...
                else
                else
                        new_pc <= 1'b0;
                        new_pc <= 1'b0;
 
 
        //
        //
        // The debug interface
        // The debug interface
 
        generate
 
        if (AW<32)
 
        begin
        always @(posedge i_clk)
        always @(posedge i_clk)
                begin
                begin
                        o_dbg_reg <= regset[i_dbg_reg];
                        o_dbg_reg <= regset[i_dbg_reg];
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
 
                        begin
 
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
 
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
 
                        end
 
                end
 
        end else begin
 
                always @(posedge i_clk)
 
                begin
 
                        o_dbg_reg <= regset[i_dbg_reg];
 
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
 
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
 
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
 
                        begin
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
 
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
                end
                end
 
                end
 
        end endgenerate
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_cc <= { gie, sleep };
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dbg_stall <= (i_halt)&&(
                o_dbg_stall <= (i_halt)&&(
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
                        ||((~opvalid)&&(~i_rst))
                        ||((~opvalid)&&(~i_rst))
Line 1281... Line 1362...
        //
        //
        //
        //
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
 
 
 
        always @(posedge i_clk)
 
                o_debug <= {
 
                        pf_pc[7:0],
 
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
 
                        op_ce, alu_ce, mem_ce,
 
                        opA[23:20], opA[3:0],
 
                        wr_reg_vl[7:0]
 
                        };
 
 
endmodule
endmodule
 
 
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