| Line 119... |
Line 119... |
o_break,
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o_break,
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// CPU interface to the wishbone bus
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// CPU interface to the wishbone bus
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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// Accounting/CPU usage interface
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// Accounting/CPU usage interface
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o_mem_stall, o_pf_stall, o_alu_stall);
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o_op_stall, o_pf_stall, o_i_count);
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parameter RESET_ADDRESS=32'h0100000;
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parameter RESET_ADDRESS=32'h0100000;
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input i_clk, i_rst, i_interrupt;
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input i_clk, i_rst, i_interrupt;
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// Debug interface -- inputs
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// Debug interface -- inputs
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input i_halt;
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input i_halt;
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input [4:0] i_dbg_reg;
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input [4:0] i_dbg_reg;
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| Line 138... |
Line 138... |
output wire [31:0] o_wb_addr, o_wb_data;
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output wire [31:0] o_wb_addr, o_wb_data;
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// Wishbone interface -- inputs
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// Wishbone interface -- inputs
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Accounting outputs ... to help us count stalls and usage
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// Accounting outputs ... to help us count stalls and usage
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output wire o_mem_stall;
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output wire o_op_stall;
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output wire o_pf_stall;
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output wire o_pf_stall;
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output wire o_alu_stall;
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output wire o_i_count;
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// Registers
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// Registers
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reg [31:0] regset [0:31];
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reg [31:0] regset [0:31];
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|
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// Condition codes
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reg [3:0] flags, iflags; // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
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reg [3:0] flags, iflags; // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
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wire master_ce;
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wire [7:0] w_uflags, w_iflags;
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wire [7:0] w_uflags, w_iflags;
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reg step, gie, sleep, break_en;
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reg break_en, step, gie, sleep;
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|
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wire [4:0] mem_wreg;
|
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wire mem_busy, mem_rdbusy;
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|
|
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reg [31:0] pf_pc;
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// The master chip enable
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reg new_pc;
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wire master_ce;
|
|
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//
|
//
|
//
|
//
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// PIPELINE STAGE #1 :: Prefetch
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// PIPELINE STAGE #1 :: Prefetch
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// Variable declarations
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// Variable declarations
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//
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//
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wire pf_ce, dcd_stalled;
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reg [31:0] pf_pc;
|
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reg new_pc;
|
|
|
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wire dcd_stalled;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
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wire [31:0] pf_addr, pf_data;
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wire [31:0] pf_addr, pf_data;
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wire [31:0] instruction, instruction_pc;
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wire [31:0] instruction, instruction_pc;
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wire pf_valid, instruction_gie;
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wire pf_valid, instruction_gie;
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|
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| Line 229... |
Line 230... |
|
|
|
|
wire mem_ce, mem_stalled;
|
wire mem_ce, mem_stalled;
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wire mem_valid, mem_ack, mem_stall,
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wire mem_valid, mem_ack, mem_stall,
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mem_cyc, mem_stb, mem_we;
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mem_cyc, mem_stb, mem_we;
|
|
wire [4:0] mem_wreg;
|
|
|
|
wire mem_busy, mem_rdbusy;
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wire [31:0] mem_addr, mem_data, mem_result;
|
wire [31:0] mem_addr, mem_data, mem_result;
|
|
|
|
|
|
|
//
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//
|
| Line 255... |
Line 259... |
|
|
|
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
// Calculate stall conditions
|
// Calculate stall conditions
|
assign pf_ce = (~dcd_stalled);
|
|
|
|
//
|
//
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// Calculate stall conditions
|
// Calculate stall conditions
|
assign dcd_ce = (pf_valid)&&(~dcd_stalled);
|
assign dcd_ce = (pf_valid)&&(~dcd_stalled);
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| Line 298... |
Line 301... |
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
//
|
//
|
//
|
//
|
`ifdef SINGLE_FETCH
|
`ifdef SINGLE_FETCH
|
|
wire pf_ce;
|
|
|
|
assign pf_ce = (~dcd_stalled);
|
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
|
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
|
instruction, instruction_pc, instruction_gie,
|
instruction, instruction_pc, instruction_gie,
|
pf_valid,
|
pf_valid,
|
pf_cyc, pf_stb, pf_we, pf_addr,
|
pf_cyc, pf_stb, pf_we, pf_addr,
|
pf_data,
|
pf_data,
|
| Line 788... |
Line 794... |
// Do we need to all our partial results from the pipeline?
|
// Do we need to all our partial results from the pipeline?
|
// What happens when the pipeline has gie and ~gie instructions within
|
// What happens when the pipeline has gie and ~gie instructions within
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// a non-gie instruction?
|
// a non-gie instruction?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
upc <= RESET_ADDRESS;
|
|
else if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
|
upc <= wr_reg_vl;
|
upc <= wr_reg_vl;
|
else if ((alu_gie)&&(alu_pc_valid))
|
else if ((alu_gie)&&(alu_pc_valid))
|
upc <= alu_pc;
|
upc <= alu_pc;
|
else if ((i_halt)&&(i_dbg_we)
|
else if ((i_halt)&&(i_dbg_we)
|
&&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
|
&&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
|
| Line 821... |
Line 825... |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
pf_pc <= wr_reg_vl;
|
pf_pc <= wr_reg_vl;
|
else if ((i_halt)&&(i_dbg_we)
|
else if ((i_halt)&&(i_dbg_we)
|
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
|
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
|
pf_pc <= i_dbg_data;
|
pf_pc <= i_dbg_data;
|
// else if (pf_ce)
|
|
else if (dcd_ce)
|
else if (dcd_ce)
|
pf_pc <= pf_pc + 1;
|
pf_pc <= pf_pc + 1;
|
|
|
initial new_pc = 1'b1;
|
initial new_pc = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 863... |
Line 866... |
//
|
//
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
// later evaluate how well we are doing.
|
// later evaluate how well we are doing.
|
//
|
//
|
//
|
//
|
assign o_mem_stall = (~i_halt)&&(~sleep)&&(opvalid)&&(mem_busy)
|
assign o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
|
&&(~pf_cyc);
|
assign o_pf_stall = (master_ce)&&(~pf_valid);
|
assign o_pf_stall = (~i_halt)&&(~sleep)&&(((pf_ce)&&(~pf_valid))
|
assign o_i_count = alu_pc_valid;
|
||((opvalid)&&(mem_busy)&&(pf_cyc)));
|
|
// assign o_alu_stall = (~i_halt)&&(~sleep)&&(~mem_busy)&&
|
|
// ((alu_stall)||(~alu_valid));
|
|
assign o_alu_stall = alu_pc_valid;
|
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
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