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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 3 and 9

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Rev 3 Rev 9
Line 119... Line 119...
                        o_break,
                        o_break,
                // CPU interface to the wishbone bus
                // CPU interface to the wishbone bus
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                // Accounting/CPU usage interface
                // Accounting/CPU usage interface
                o_mem_stall, o_pf_stall, o_alu_stall);
                o_op_stall, o_pf_stall, o_i_count);
        parameter       RESET_ADDRESS=32'h0100000;
        parameter       RESET_ADDRESS=32'h0100000;
        input                   i_clk, i_rst, i_interrupt;
        input                   i_clk, i_rst, i_interrupt;
        // Debug interface -- inputs
        // Debug interface -- inputs
        input                   i_halt;
        input                   i_halt;
        input           [4:0]    i_dbg_reg;
        input           [4:0]    i_dbg_reg;
Line 138... Line 138...
        output  wire    [31:0]   o_wb_addr, o_wb_data;
        output  wire    [31:0]   o_wb_addr, o_wb_data;
        // Wishbone interface -- inputs
        // Wishbone interface -- inputs
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        // Accounting outputs ... to help us count stalls and usage
        // Accounting outputs ... to help us count stalls and usage
        output  wire            o_mem_stall;
        output  wire            o_op_stall;
        output  wire            o_pf_stall;
        output  wire            o_pf_stall;
        output  wire            o_alu_stall;
        output  wire            o_i_count;
 
 
 
 
        // Registers
        // Registers
        reg     [31:0]   regset [0:31];
        reg     [31:0]   regset [0:31];
 
 
 
        // Condition codes
        reg     [3:0]    flags, iflags;  // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        reg     [3:0]    flags, iflags;  // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
        wire            master_ce;
 
        wire    [7:0]    w_uflags, w_iflags;
        wire    [7:0]    w_uflags, w_iflags;
        reg             step, gie, sleep, break_en;
        reg             break_en, step, gie, sleep;
 
 
        wire    [4:0]    mem_wreg;
 
        wire            mem_busy, mem_rdbusy;
 
 
 
        reg     [31:0]   pf_pc;
        // The master chip enable
        reg             new_pc;
        wire            master_ce;
 
 
        //
        //
        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //              Variable declarations
        //              Variable declarations
        //
        //
        wire            pf_ce, dcd_stalled;
        reg     [31:0]   pf_pc;
 
        reg             new_pc;
 
 
 
        wire            dcd_stalled;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
        wire    [31:0]   pf_addr, pf_data;
        wire    [31:0]   pf_addr, pf_data;
        wire    [31:0]   instruction, instruction_pc;
        wire    [31:0]   instruction, instruction_pc;
        wire    pf_valid, instruction_gie;
        wire    pf_valid, instruction_gie;
 
 
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        wire    mem_ce, mem_stalled;
        wire    mem_ce, mem_stalled;
        wire    mem_valid, mem_ack, mem_stall,
        wire    mem_valid, mem_ack, mem_stall,
                mem_cyc, mem_stb, mem_we;
                mem_cyc, mem_stb, mem_we;
 
        wire    [4:0]    mem_wreg;
 
 
 
        wire            mem_busy, mem_rdbusy;
        wire    [31:0]   mem_addr, mem_data, mem_result;
        wire    [31:0]   mem_addr, mem_data, mem_result;
 
 
 
 
 
 
        //
        //
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        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign          pf_ce = (~dcd_stalled);
 
 
 
        //
        //
        //      PIPELINE STAGE #2 :: Instruction Decode
        //      PIPELINE STAGE #2 :: Instruction Decode
        //              Calculate stall conditions
        //              Calculate stall conditions
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
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        //
        //
        //      PIPELINE STAGE #1 :: Prefetch
        //      PIPELINE STAGE #1 :: Prefetch
        //
        //
        //
        //
`ifdef  SINGLE_FETCH
`ifdef  SINGLE_FETCH
 
        wire            pf_ce;
 
 
 
        assign          pf_ce = (~dcd_stalled);
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
                                instruction, instruction_pc, instruction_gie,
                                instruction, instruction_pc, instruction_gie,
                                        pf_valid,
                                        pf_valid,
                                pf_cyc, pf_stb, pf_we, pf_addr,
                                pf_cyc, pf_stb, pf_we, pf_addr,
                                        pf_data,
                                        pf_data,
Line 788... Line 794...
        // Do we need to all our partial results from the pipeline?
        // Do we need to all our partial results from the pipeline?
        // What happens when the pipeline has gie and ~gie instructions within
        // What happens when the pipeline has gie and ~gie instructions within
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // it?  Do we clear both?  What if a gie instruction tries to clear
        // a non-gie instruction?
        // a non-gie instruction?
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
                        upc <= RESET_ADDRESS;
 
                else if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
 
                        upc <= wr_reg_vl;
                        upc <= wr_reg_vl;
                else if ((alu_gie)&&(alu_pc_valid))
                else if ((alu_gie)&&(alu_pc_valid))
                        upc <= alu_pc;
                        upc <= alu_pc;
                else if ((i_halt)&&(i_dbg_we)
                else if ((i_halt)&&(i_dbg_we)
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
Line 821... Line 825...
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
                        pf_pc <= wr_reg_vl;
                        pf_pc <= wr_reg_vl;
                else if ((i_halt)&&(i_dbg_we)
                else if ((i_halt)&&(i_dbg_we)
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
                        pf_pc <= i_dbg_data;
                        pf_pc <= i_dbg_data;
                // else if (pf_ce)
 
                else if (dcd_ce)
                else if (dcd_ce)
                        pf_pc <= pf_pc + 1;
                        pf_pc <= pf_pc + 1;
 
 
        initial new_pc = 1'b1;
        initial new_pc = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
Line 863... Line 866...
        //
        //
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // Produce accounting outputs: Account for any CPU stalls, so we can
        // later evaluate how well we are doing.
        // later evaluate how well we are doing.
        //
        //
        //
        //
        assign  o_mem_stall  = (~i_halt)&&(~sleep)&&(opvalid)&&(mem_busy)
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
                                        &&(~pf_cyc);
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
        assign  o_pf_stall   = (~i_halt)&&(~sleep)&&(((pf_ce)&&(~pf_valid))
        assign  o_i_count  = alu_pc_valid;
                                        ||((opvalid)&&(mem_busy)&&(pf_cyc)));
 
        // assign       o_alu_stall  = (~i_halt)&&(~sleep)&&(~mem_busy)&&
 
                                        // ((alu_stall)||(~alu_valid));
 
        assign  o_alu_stall  = alu_pc_valid;
 
endmodule
endmodule
 
 
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