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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 83 and 91

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Rev 83 Rev 91
Line 738... Line 738...
        wire    w_opvalid;
        wire    w_opvalid;
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid);
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid);
        initial opvalid     = 1'b0;
        initial opvalid     = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_alu = 1'b0;
        initial opvalid_mem = 1'b0;
        initial opvalid_mem = 1'b0;
 
        initial opvalid_div = 1'b0;
 
        initial opvalid_fpu = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        opvalid     <= 1'b0;
                        opvalid     <= 1'b0;
                        opvalid_alu <= 1'b0;
                        opvalid_alu <= 1'b0;
Line 967... Line 969...
                                ||((opF_wr)&&(dcdB_cc))
                                ||((opF_wr)&&(dcdB_cc))
                                // Stall on any ongoing memory operation that
                                // Stall on any ongoing memory operation that
                                // will write to opB -- captured above
                                // will write to opB -- captured above
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
                                );
                                );
`else
 
        // No stalls without pipelining, 'cause how can you have a pipeline
 
        // hazard without the pipeline?
 
        assign  dcdB_stall = 1'b0;
 
`endif
 
        assign  dcdF_stall = ((~dcdF[3])
        assign  dcdF_stall = ((~dcdF[3])
                                        ||((dcdA_rd)&&(dcdA_cc))
                                        ||((dcdA_rd)&&(dcdA_cc))
                                        ||((dcdB_rd)&&(dcdB_cc)))
                                        ||((dcdB_rd)&&(dcdB_cc)))
                                        &&(opvalid)&&(opR_cc);
                                        &&(opvalid)&&(opR_cc);
                                // &&(dcdvalid) is checked for elsewhere
                                // &&(dcdvalid) is checked for elsewhere
 
`else
 
        // No stalls without pipelining, 'cause how can you have a pipeline
 
        // hazard without the pipeline?
 
        assign  dcdB_stall = 1'b0;
 
        assign  dcdF_stall = 1'b0;
 
`endif
        //
        //
        //
        //
        //      PIPELINE STAGE #4 :: Apply Instruction
        //      PIPELINE STAGE #4 :: Apply Instruction
        //
        //
        //
        //

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