OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [cpudefs.v] - Diff between revs 184 and 193

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 184 Rev 193
Line 26... Line 26...
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 74... Line 74...
// includes the multiply.  (This parameter may still be overridden, as with
// includes the multiply.  (This parameter may still be overridden, as with
// any parameter ...)  If the multiply is not included and
// any parameter ...)  If the multiply is not included and
// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
// instruction that will then trip the illegal instruction trap.
// instruction that will then trip the illegal instruction trap.
//
//
 
// Either not defining this value, or defining it to zero will disable the
 
// hardware multiply.  A value of '1' will cause the multiply to occurr in one
 
// clock cycle only--often at the expense of the rest of the CPUs speed.
 
// A value of 2 will cause the multiply to have a single delay cycle, 3 will
 
// have two delay cycles, and 4 (or more) will have 3 delay cycles.
//
//
`define OPT_MULTIPLY    1
//
 
`define OPT_MULTIPLY    3
//
//
//
//
//
//
// OPT_DIVIDE controls whether or not the divide instruction is built and
// OPT_DIVIDE controls whether or not the divide instruction is built and
// included into the ZipCPU by default.  Set this option and a parameter will
// included into the ZipCPU by default.  Set this option and a parameter will

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.