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[/] [zipcpu/] [trunk/] [rtl/] [cpudefs.v] - Diff between revs 193 and 201

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///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    cpudefs.v
// Filename:    cpudefs.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
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//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
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// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
 
//
 
//
`ifndef CPUDEFS_H
`ifndef CPUDEFS_H
`define CPUDEFS_H
`define CPUDEFS_H
//
//
//
//
// The first couple options control the Zip CPU instruction set, and how
// The first couple options control the Zip CPU instruction set, and how
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//
//
// `define      OPT_IMPLEMENT_FPU
// `define      OPT_IMPLEMENT_FPU
//
//
//
//
//
//
// OPT_NEW_INSTRUCTION_SET controls whether or not the new instruction set
 
// is in use.  The new instruction set contains space for floating point
 
// operations, signed and unsigned divide instructions, as well as bit reversal
 
// and ... at least two other operations yet to be defined.  The decoder alone
 
// uses about 70 fewer LUTs, although in practice this works out to 12 fewer
 
// when all works out in the wash.  Further, floating point and divide
 
// instructions will cause an illegal instruction exception if they are not
 
// implemented--so software capability can be built to use these instructions
 
// immediately, even if the hardware is not yet ready.
 
//
 
// This option is likely to go away in the future, obsoleting the previous
 
// instruction set, so I recommend setting this option and switching to the
 
// new instruction set as soon as possible.
 
//
 
`define OPT_NEW_INSTRUCTION_SET
 
//
 
//
 
//
 
//
 
//
 
//
//
// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and 
// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and 
// whether or not it can issue one instruction per clock.  When set, the
// whether or not it can issue one instruction per clock.  When set, the
// prefetch has no cache, and only one instruction is fetched at a time.
// prefetch has no cache, and only one instruction is fetched at a time.
// This effectively sets the CPU so that only one instruction is ever 
// This effectively sets the CPU so that only one instruction is ever 
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//
//
`define OPT_PIPELINED_BUS_ACCESS
`define OPT_PIPELINED_BUS_ACCESS
//
//
//
//
//
//
`ifdef  OPT_NEW_INSTRUCTION_SET
 
//
//
//
//
//
// The instruction set defines an optional compressed instruction set (CIS)
// The new instruction set also defines a set of very long instruction words.
// complement.  These were at one time erroneously called Very Long Instruction
// Well, calling them "very long" instruction words is probably a misnomer,
// Words.  They are more appropriately referred to as compressed instructions.
// although we're going to do it.  They're really 2x16-bit instructions---
// The compressed instruction format allows two instructions to be packed into
// instruction words that pack two instructions into one word.  (2x14 bit
// the same instruction word.  Some instructions can be compressed, not all.
// really--'cause you need a bit to note the instruction is a 2x instruction,
// Compressed instructions take the same time to complete.  Set OPT_CIS to
// and then 3-bits for the condition codes ...)  Set OPT_VLIW to include these
// include these double instructions as part of the instruction set.  These
// double instructions as part of the new instruction set.  These allow a single
// instructions are designed to get more code density from the instruction set,
// instruction to contain two instructions within.   These instructions are
// and to hopefully take some pain off of the performance of the pre-fetch and
// designed to get more code density from the instruction set, and to hopefully
// instruction cache.
// take some pain off of the performance of the pre-fetch and instruction cache.
 
//
//
// These new instructions, however, also necessitate a change in the Zip
// These new instructions, however, also necessitate a change in the Zip
// CPU--the Zip CPU can no longer execute instructions atomically.  It must
// CPU--the Zip CPU can no longer execute instructions atomically.  It must
// now execute non-VLIW instructions, or VLIW instruction pairs, atomically. 
// now execute non-CIS instructions, or CIS instruction pairs, atomically. 
// This logic has been added into the ZipCPU, but it has not (yet) been
// This logic has been added into the ZipCPU, but it has not (yet) been
// tested thoroughly.
// tested thoroughly.
//
//
// Oh, and the assembler, the debugger, and the object file dumper, and the
 
// simulator all need to be updated as well ....
 
//
 
`define OPT_VLIW
 
//
//
 
`define OPT_CIS
//
//
`endif // OPT_NEW_INSTRUCTION_SET
 
//
//
//
//
`endif  // OPT_SINGLE_FETCH
`endif  // OPT_SINGLE_FETCH
//
//
//
//

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