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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [icontrol.v] - Diff between revs 2 and 69

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Line 46... Line 46...
//      To get access to more than 15 interrupts, chain these together, so
//      To get access to more than 15 interrupts, chain these together, so
//      that one interrupt controller device feeds another.
//      that one interrupt controller device feeds another.
//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
Line 69... Line 69...
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
module  icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus,
module  icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus,
                i_brd_ints, o_interrupt_strobe);
                i_brd_ints, o_interrupt);
        parameter       IUSED = 15;
        parameter       IUSED = 15;
        input                   i_clk, i_reset;
        input                   i_clk, i_reset;
        input                   i_wr;
        input                   i_wr;
        input           [31:0]   i_proc_bus;
        input           [31:0]   i_proc_bus;
        output  wire    [31:0]   o_proc_bus;
        output  wire    [31:0]   o_proc_bus;
        input           [(IUSED-1):0]    i_brd_ints;
        input           [(IUSED-1):0]    i_brd_ints;
        output  reg             o_interrupt_strobe;
        output  wire            o_interrupt;
 
 
        reg     [(IUSED-1):0]    r_int_state;
        reg     [(IUSED-1):0]    r_int_state;
        reg     [(IUSED-1):0]    r_int_enable;
        reg     [(IUSED-1):0]    r_int_enable;
        wire    [(IUSED-1):0]    nxt_int_state;
        wire    [(IUSED-1):0]    nxt_int_state;
        reg             r_any, r_interrupt, r_gie;
        reg             r_any, r_interrupt, r_gie;
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                                r_any, { {(15-IUSED){1'b0}}, r_int_state  } };
                                r_any, { {(15-IUSED){1'b0}}, r_int_state  } };
        end else begin
        end else begin
                assign o_proc_bus = { r_gie, r_int_enable, r_any, r_int_state };
                assign o_proc_bus = { r_gie, r_int_enable, r_any, r_int_state };
        end endgenerate
        end endgenerate
 
 
        reg     int_condition;
        /*
        initial int_condition      = 1'b0;
        reg     int_condition;
        initial o_interrupt_strobe = 1'b0;
        initial int_condition      = 1'b0;
        always @(posedge i_clk)
        initial o_interrupt_strobe = 1'b0;
                if (i_reset)
        always @(posedge i_clk)
                begin
                if (i_reset)
                        int_condition <= 1'b0;
                begin
                        o_interrupt_strobe <= 1'b0;
                        int_condition <= 1'b0;
                end else if (~r_interrupt) // This might end up generating
                        o_interrupt_strobe <= 1'b0;
                begin // many, many, (wild many) interrupts
                end else if (~r_interrupt) // This might end up generating
                        int_condition <= 1'b0;
                begin // many, many, (wild many) interrupts
                        o_interrupt_strobe <= 1'b0;
                        int_condition <= 1'b0;
                end else if ((~int_condition)&&(r_interrupt))
                        o_interrupt_strobe <= 1'b0;
                begin
                end else if ((~int_condition)&&(r_interrupt))
                        int_condition <= 1'b1;
                begin
                        o_interrupt_strobe <= 1'b1;
                        int_condition <= 1'b1;
                end else
                        o_interrupt_strobe <= 1'b1;
                        o_interrupt_strobe <= 1'b0;
                end else
 
                        o_interrupt_strobe <= 1'b0;
 
        */
 
 
 
        assign  o_interrupt = r_interrupt;
 
 
endmodule
endmodule
 
 
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