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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Diff between revs 88 and 160

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Rev 88 Rev 160
Line 79... Line 79...
//              register.
//              register.
//
//
// Creator:     Dan Gisselquist
// Creator:     Dan Gisselquist
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
// Copyright:   2015
 
//
 
//
 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 103... Line 100...
//
//
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
//
//
module wbdmac(i_clk,
`define DMA_IDLE        3'b000
 
`define DMA_WAIT        3'b001
 
`define DMA_READ_REQ    3'b010
 
`define DMA_READ_ACK    3'b011
 
`define DMA_PRE_WRITE   3'b100
 
`define DMA_WRITE_REQ   3'b101
 
`define DMA_WRITE_ACK   3'b110
 
 
 
module wbdmac(i_clk, i_rst,
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
                        o_swb_ack, o_swb_stall, o_swb_data,
                        o_swb_ack, o_swb_stall, o_swb_data,
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
                i_dev_ints,
                i_dev_ints,
                o_interrupt);
                o_interrupt);
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
        input                   i_clk;
        input                   i_clk, i_rst;
        // Slave/control wishbone inputs
        // Slave/control wishbone inputs
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
        input   [1:0]            i_swb_addr;
        input   [1:0]            i_swb_addr;
        input   [(DW-1):0]       i_swb_data;
        input   [(DW-1):0]       i_swb_data;
        // Slave/control wishbone outputs
        // Slave/control wishbone outputs
        output  reg             o_swb_ack;
        output  reg             o_swb_ack;
        output  wire            o_swb_stall;
        output  wire            o_swb_stall;
        output  reg [(DW-1):0]   o_swb_data;
        output  reg [(DW-1):0]   o_swb_data;
        // Master/DMA wishbone control
        // Master/DMA wishbone control
        output  reg             o_mwb_cyc, o_mwb_stb, o_mwb_we;
        output  wire            o_mwb_cyc, o_mwb_stb, o_mwb_we;
        output  reg [(AW-1):0]   o_mwb_addr;
        output  reg [(AW-1):0]   o_mwb_addr;
        output  reg [(DW-1):0]   o_mwb_data;
        output  reg [(DW-1):0]   o_mwb_data;
        // Master/DMA wishbone responses from the bus
        // Master/DMA wishbone responses from the bus
        input                   i_mwb_ack, i_mwb_stall;
        input                   i_mwb_ack, i_mwb_stall;
        input   [(DW-1):0]       i_mwb_data;
        input   [(DW-1):0]       i_mwb_data;
Line 143... Line 148...
        //
        //
        // input                        i_other_busmaster_requests_bus;
        // input                        i_other_busmaster_requests_bus;
        //
        //
 
 
 
 
        reg                     cfg_wp; // Write protect
        reg     [2:0]            dma_state;
        reg                     cfg_err;
        reg                     cfg_err, cfg_len_nonzero;
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
        reg                     cfg_incs, cfg_incd;
        reg                     cfg_incs, cfg_incd;
        reg     [(LGDV-1):0]     cfg_dev_trigger;
        reg     [(LGDV-1):0]     cfg_dev_trigger;
        reg                     cfg_on_dev_trigger;
        reg                     cfg_on_dev_trigger;
 
 
        // Single block operations: We'll read, then write, up to a single
        // Single block operations: We'll read, then write, up to a single
        // memory block here.
        // memory block here.
 
 
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
        reg     [(LGMEMLEN):0]   nread, nwritten, nacks;
        reg     [(LGMEMLEN):0]   nread, nwritten, nwacks, nracks;
        wire    [(AW-1):0]       bus_nacks;
        wire    [(AW-1):0]       bus_nracks;
        assign  bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };
        assign  bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };
 
 
 
        reg     last_read_request, last_read_ack,
 
                last_write_request, last_write_ack;
 
        reg     trigger, abort;
 
 
 
        initial dma_state = `DMA_IDLE;
        initial o_interrupt = 1'b0;
        initial o_interrupt = 1'b0;
        initial o_mwb_cyc   = 1'b0;
 
        initial cfg_err     = 1'b0;
 
        initial cfg_wp      = 1'b0;
 
        initial cfg_len     = {(AW){1'b0}};
        initial cfg_len     = {(AW){1'b0}};
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
        initial cfg_on_dev_trigger = 1'b0;
        initial cfg_on_dev_trigger = 1'b0;
 
        initial cfg_len_nonzero = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
        case(dma_state)
 
        `DMA_IDLE: begin
 
                o_mwb_addr <= cfg_raddr;
 
                nwritten   <= 0;
 
                nread      <= 0;
 
                nracks     <= 0;
 
                nwacks     <= 0;
 
                cfg_len_nonzero <= (|cfg_len);
 
 
 
                // When the slave wishbone writes, and we are in this 
 
                // (ready) configuration, then allow the DMA to be controlled
 
                // and thus to start.
 
                if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))
                begin
                begin
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                        case(i_swb_addr)
 
                        2'b00: begin
 
                                if ((i_swb_data[27:16] == 12'hfed)
 
                                                &&(cfg_len_nonzero))
 
                                        dma_state <= `DMA_WAIT;
 
                                cfg_blocklen_sub_one
 
                                        <= i_swb_data[(LGMEMLEN-1):0]
 
                                        + {(LGMEMLEN){1'b1}};
 
                                        // i.e. -1;
 
                                cfg_dev_trigger    <= i_swb_data[14:10];
 
                                cfg_on_dev_trigger <= i_swb_data[15];
 
                                cfg_incs  <= ~i_swb_data[29];
 
                                cfg_incd  <= ~i_swb_data[28];
 
                                end
 
                        2'b01: begin
 
                                cfg_len   <=  i_swb_data[(AW-1):0];
 
                                cfg_len_nonzero <= (|i_swb_data[(AW-1):0]);
 
                                end
 
                        2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
 
                        2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
 
                        endcase
 
                end end
 
        `DMA_WAIT: begin
 
                o_mwb_addr <= cfg_raddr;
 
                nracks     <= 0;
 
                nwacks     <= 0;
 
                nwritten   <= 0;
 
                nread      <= 0;
 
                if (abort)
 
                        dma_state <= `DMA_IDLE;
 
                else if (trigger)
 
                        dma_state <= `DMA_READ_REQ;
 
                end
 
        `DMA_READ_REQ: begin
 
                nwritten  <= 0;
 
 
 
                if (~i_mwb_stall)
                        begin
                        begin
                                nwritten <= nwritten+1;
                        // Number of read acknowledgements needed
                                if (nwritten == nread-1)
                        nracks <= nracks+1;
 
                        if (last_read_request)
 
        //((nracks == {1'b0, cfg_blocklen_sub_one})||(bus_nracks == cfg_len-1))
                                        // Wishbone interruptus
                                        // Wishbone interruptus
                                        o_mwb_stb <= 1'b0;
                                dma_state <= `DMA_READ_ACK;
                                else if (cfg_incd) begin
                        if (cfg_incs)
                                        o_mwb_addr <= o_mwb_addr + 1;
                                o_mwb_addr <= o_mwb_addr
                                        cfg_waddr  <= cfg_waddr  + 1;
                                                + {{(AW-1){1'b0}},1'b1};
                                end
                                end
                                // o_mwb_data <= dma_mem[nwritten + 1];
 
 
                if (i_mwb_err)
 
                begin
 
                        cfg_len <= 0;
 
                        dma_state <= `DMA_IDLE;
                        end
                        end
 
                if (abort)
 
                        dma_state <= `DMA_IDLE;
 
                if (i_mwb_ack)
 
                begin
 
                        nread <= nread+1;
 
                        if (cfg_incs)
 
                                cfg_raddr  <= cfg_raddr
 
                                                + {{(AW-1){1'b0}},1'b1};
 
                end end
 
        `DMA_READ_ACK: begin
 
                nwritten  <= 0;
 
 
                        if (i_mwb_err)
                        if (i_mwb_err)
                        begin
                        begin
                                o_mwb_cyc <= 1'b0;
 
                                cfg_err <= 1'b1;
 
                                cfg_len <= 0;
                                cfg_len <= 0;
                                nread   <= 0;
                        dma_state <= `DMA_IDLE;
                        end else if (i_mwb_ack)
                        end else if (i_mwb_ack)
                        begin
                        begin
                                nacks <= nacks+1;
                        nread <= nread+1;
                                cfg_len <= cfg_len - 1;
                        if (last_read_ack) // (nread+1 == nracks)
                                if ((nacks+1 == nwritten)&&(~o_mwb_stb))
                                dma_state  <= `DMA_PRE_WRITE;
                                begin
                        if (cfg_incs)
                                        o_mwb_cyc <= 1'b0;
                                cfg_raddr  <= cfg_raddr
                                        nread <= 0;
                                                + {{(AW-1){1'b0}},1'b1};
                                        o_interrupt <= (cfg_len == 1);
 
                                        // Turn write protect back on
 
                                        cfg_wp    <= 1'b1;
 
                                end
                                end
 
                if (abort)
 
                        dma_state <= `DMA_IDLE;
                        end
                        end
                end else if ((o_mwb_cyc)&&(~o_mwb_we)) // Read cycle
        `DMA_PRE_WRITE: begin
                begin
                o_mwb_addr <= cfg_waddr;
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                dma_state <= (abort)?`DMA_IDLE:`DMA_WRITE_REQ;
 
                end
 
        `DMA_WRITE_REQ: begin
 
                if (~i_mwb_stall)
                        begin
                        begin
                                nacks <= nacks+1;
                        nwritten <= nwritten+1;
                                if ((nacks == {1'b0, cfg_blocklen_sub_one})
                        if (last_write_request) // (nwritten == nread-1)
                                        ||(bus_nacks <= cfg_len-1))
 
                                        // Wishbone interruptus
                                        // Wishbone interruptus
                                        o_mwb_stb <= 1'b0;
                                dma_state <= `DMA_WRITE_ACK;
                                else if (cfg_incs) begin
                        if (cfg_incd)
                                        o_mwb_addr <= o_mwb_addr + 1;
                        begin
 
                                o_mwb_addr <= o_mwb_addr
 
                                                + {{(AW-1){1'b0}},1'b1};
 
                                cfg_waddr  <= cfg_waddr
 
                                                + {{(AW-1){1'b0}},1'b1};
                                end
                                end
                        end
                        end
 
 
                        if (i_mwb_err)
                        if (i_mwb_err)
                        begin
                        begin
                                o_mwb_cyc <= 1'b0;
 
                                cfg_err <= 1'b1;
 
                                cfg_len <= 0;
                                cfg_len <= 0;
                                nread <= 0;
                        dma_state <= `DMA_IDLE;
                        end else if (i_mwb_ack)
                end
                        begin
                if (i_mwb_ack)
                                nread <= nread+1;
 
                                if ((~o_mwb_stb)&&(nread+1 == nacks))
 
                                begin
                                begin
                                        o_mwb_cyc <= 1'b0;
                        nwacks <= nwacks+1;
                                        nacks <= 0;
                        cfg_len <= cfg_len +{(AW){1'b1}}; // -1
                                end
                                end
                                if (cfg_incs)
                if (abort)
                                        cfg_raddr  <= cfg_raddr  + 1;
                        dma_state <= `DMA_IDLE;
                                // dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
 
                        end
                        end
                end else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
        `DMA_WRITE_ACK: begin
                begin // Initiate/continue a write cycle
                if (i_mwb_err)
                        o_mwb_cyc  <= 1'b1;
                begin
                        o_mwb_stb  <= 1'b1;
                        cfg_len  <= 0;
                        o_mwb_we   <= 1'b1;
 
                        // o_mwb_data <= dma_mem[0];
 
                        o_mwb_addr <= cfg_waddr;
 
                        // nwritten  <= 0; // Can't set to zero, in case we're
 
                        // nacks     <= 0; //   continuing a cycle
 
                end else if ((~o_mwb_cyc)&&(nread == 0)&&(cfg_len>0)&&(~cfg_wp)
 
                                &&((~cfg_on_dev_trigger)
 
                                        ||(i_dev_ints[cfg_dev_trigger])))
 
                begin // Initiate a read cycle
 
                        o_mwb_cyc <= 1'b1;
 
                        o_mwb_stb <= 1'b1;
 
                        o_mwb_we  <= 1'b0;
 
                        o_mwb_addr<= cfg_raddr;
 
                        nwritten  <= 0;
 
                        nread     <= 0;
                        nread     <= 0;
                        nacks     <= 0;
                        dma_state <= `DMA_IDLE;
                end else begin
                end else if (i_mwb_ack)
                        o_mwb_cyc  <= 1'b0;
 
                        o_mwb_stb  <= 1'b0;
 
                        o_mwb_we   <= 1'b0;
 
                        o_mwb_addr <= cfg_raddr;
 
                        o_interrupt<= 1'b0;
 
                        nwritten   <= 0;
 
                        if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))
 
                        begin
                        begin
                                cfg_wp <= 1'b1;
                        nwacks <= nwacks+1;
                                case(i_swb_addr)
                        cfg_len <= cfg_len +{(AW){1'b1}};//cfg_len -= 1;
                                2'b00: begin
                        if (last_write_ack) // (nwacks+1 == nwritten)
                                        cfg_wp    <= (i_swb_data[27:16]!=12'hfed);
                        begin
                                        cfg_blocklen_sub_one
                                nread <= 0;
                                                <= i_swb_data[(LGMEMLEN-1):0]
                                dma_state <= (cfg_len == 1)?`DMA_IDLE:`DMA_WAIT;
                                                + {(LGMEMLEN){1'b1}};
 
                                                // i.e. -1;
 
                                        cfg_dev_trigger    <= i_swb_data[14:10];
 
                                        cfg_on_dev_trigger <= i_swb_data[15];
 
                                        cfg_incs  <= ~i_swb_data[29];
 
                                        cfg_incd  <= ~i_swb_data[28];
 
                                        cfg_err   <= 1'b0;
 
                                        end
                                        end
                                2'b01: cfg_len   <=  i_swb_data[(AW-1):0];
 
                                2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
 
                                2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
 
                                endcase
 
                        end
                        end
 
 
 
                if (abort)
 
                        dma_state <= `DMA_IDLE;
                end
                end
 
        default:
 
                dma_state <= `DMA_IDLE;
 
        endcase
 
 
 
        initial o_interrupt = 1'b0;
 
        always @(posedge i_clk)
 
                o_interrupt <= (dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack)
 
                                &&(last_write_ack)
 
                                &&(cfg_len == {{(AW-1){1'b0}},1'b1});
 
 
 
        initial cfg_err = 1'b0;
 
        always @(posedge i_clk)
 
                if (dma_state == `DMA_IDLE)
 
                begin
 
                        if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)
 
                                        &&(i_swb_addr==2'b00))
 
                                cfg_err <= 1'b0;
 
                end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort))
 
                        cfg_err <= 1'b1;
 
 
 
        initial last_read_request = 1'b0;
 
        always @(posedge i_clk)
 
                if ((dma_state == `DMA_WAIT)||(dma_state == `DMA_READ_REQ))
 
                begin
 
                        if ((~i_mwb_stall)&&(dma_state == `DMA_READ_REQ))
 
                        begin
 
                                last_read_request <=
 
                                (nracks + 1 == { 1'b0, cfg_blocklen_sub_one})
 
                                        ||(bus_nracks == cfg_len-2);
 
                        end else
 
                                last_read_request <=
 
                                        (nracks== { 1'b0, cfg_blocklen_sub_one})
 
                                        ||(bus_nracks == cfg_len-1);
 
                end else
 
                        last_read_request <= 1'b0;
 
 
 
        initial last_read_ack = 1'b0;
 
        always @(posedge i_clk)
 
                if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
 
                begin
 
                        if (i_mwb_ack)
 
                                last_read_ack <= (nread+2 == nracks);
 
                        else
 
                                last_read_ack <= (nread+1 == nracks);
 
                end else
 
                        last_read_ack <= 1'b0;
 
 
 
        initial last_write_request = 1'b0;
 
        always @(posedge i_clk)
 
                if (dma_state == `DMA_PRE_WRITE)
 
                        last_write_request <= (nread <= 1);
 
                else if (dma_state == `DMA_WRITE_REQ)
 
                begin
 
                        if (i_mwb_stall)
 
                                last_write_request <= (nwritten >= nread-1);
 
                        else
 
                                last_write_request <= (nwritten >= nread-2);
 
                end else
 
                        last_write_request <= 1'b0;
 
 
 
        initial last_write_ack = 1'b0;
 
        always @(posedge i_clk)
 
                if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK))
 
                begin
 
                        if (i_mwb_ack)
 
                                last_write_ack <= (nwacks+2 == nwritten);
 
                        else
 
                                last_write_ack <= (nwacks+1 == nwritten);
 
                end else
 
                        last_write_ack <= 1'b0;
 
 
 
        assign  o_mwb_cyc = (dma_state == `DMA_READ_REQ)
 
                        ||(dma_state == `DMA_READ_ACK)
 
                        ||(dma_state == `DMA_WRITE_REQ)
 
                        ||(dma_state == `DMA_WRITE_ACK);
 
 
 
        assign  o_mwb_stb = (dma_state == `DMA_READ_REQ)
 
                        ||(dma_state == `DMA_WRITE_REQ);
 
 
 
        assign  o_mwb_we = (dma_state == `DMA_PRE_WRITE)
 
                        ||(dma_state == `DMA_WRITE_REQ)
 
                        ||(dma_state == `DMA_WRITE_ACK);
 
 
        //
        //
        // This is tricky.  In order for Vivado to consider dma_mem to be a 
        // This is tricky.  In order for Vivado to consider dma_mem to be a 
        // proper memory, it must have a simple address fed into it.  Hence
        // proper memory, it must have a simple address fed into it.  Hence
        // the read_address (rdaddr) register.  The problem is that this
        // the read_address (rdaddr) register.  The problem is that this
        // register must always be one greater than the address we actually
        // register must always be one greater than the address we actually
        // want to read from, unless we are idling.  So ... the math is touchy.
        // want to read from, unless we are idling.  So ... the math is touchy.
        //
        //
        reg     [(LGMEMLEN-1):0] rdaddr;
        reg     [(LGMEMLEN-1):0] rdaddr;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_mwb_cyc)&&(o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall))
                if((dma_state == `DMA_IDLE)||(dma_state == `DMA_WAIT)
                        // This would be the normal advance, save that we are
                                ||(dma_state == `DMA_WRITE_ACK))
                        // already one ahead of nwritten
                        rdaddr <= 0;
                        rdaddr <= rdaddr + 1; // {{(LGMEMLEN-1){1'b0}},1};
                else if ((dma_state == `DMA_PRE_WRITE)
                else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
                                ||((dma_state==`DMA_WRITE_REQ)&&(~i_mwb_stall)))
                        // Here's where we do our extra advance
                        rdaddr <= rdaddr + {{(LGMEMLEN-1){1'b0}},1'b1};
                        rdaddr <= nwritten[(LGMEMLEN-1):0]+1;
 
                else if ((~o_mwb_cyc)||(~o_mwb_we))
 
                        rdaddr <= nwritten[(LGMEMLEN-1):0];
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((~o_mwb_cyc)||((o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall)))
                if ((dma_state != `DMA_WRITE_REQ)||(~i_mwb_stall))
                        o_mwb_data <= dma_mem[rdaddr];
                        o_mwb_data <= dma_mem[rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_mwb_cyc)&&(~o_mwb_we)&&(i_mwb_ack))
                if((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                casez(i_swb_addr)
                casez(i_swb_addr)
                2'b00: o_swb_data <= {  ~cfg_wp, cfg_err,
                2'b00: o_swb_data <= {  (dma_state != `DMA_IDLE), cfg_err,
                                        ~cfg_incs, ~cfg_incd,
                                        ~cfg_incs, ~cfg_incd,
                                        1'b0, nread,
                                        1'b0, nread,
                                        cfg_on_dev_trigger, cfg_dev_trigger,
                                        cfg_on_dev_trigger, cfg_dev_trigger,
                                        cfg_blocklen_sub_one
                                        cfg_blocklen_sub_one
                                        };
                                        };
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
                endcase
                endcase
 
 
 
        // This causes us to wait a minimum of two clocks before starting: One
 
        // to go into the wait state, and then one while in the wait state to
 
        // develop the trigger.
 
        initial trigger = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
                trigger <=  (dma_state == `DMA_WAIT)
                        o_swb_ack <= 1'b1;
                                &&((~cfg_on_dev_trigger)
                // else if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)&&(~o_mwb_cyc)&&(nread == 0))
                                        ||(i_dev_ints[cfg_dev_trigger]));
                else
 
                        o_swb_ack <= 1'b0;
        // Ack any access.  We'll quietly ignore any access where we are busy,
 
        // but ack it anyway.  In other words, before writing to the device,
 
        // double check that it isn't busy, and then write.
 
        always @(posedge i_clk)
 
                o_swb_ack <= (i_swb_cyc)&&(i_swb_stb);
 
 
        assign  o_swb_stall = 1'b0;
        assign  o_swb_stall = 1'b0;
 
 
 
        initial abort = 1'b0;
 
        always @(posedge i_clk)
 
                abort <= (i_rst)||((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)
 
                        &&(i_swb_addr == 2'b00)
 
                        &&(i_swb_data == 32'hffed0000));
 
 
endmodule
endmodule
 
 
 
 
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