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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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// Filename: wbdmac.v
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// Filename: wbdmac.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: Wishbone DMA controller
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// Purpose: Wishbone DMA controller
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// be read from the length register. If the internal buffer is
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// be read from the length register. If the internal buffer is
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// being used, then you can read how much has been read into that
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// being used, then you can read how much has been read into that
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// buffer by reading from bits 25..16 of this control/status
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// buffer by reading from bits 25..16 of this control/status
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// register.
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// register.
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`define DMA_IDLE 3'b000
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`define DMA_IDLE 3'b000
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`define DMA_WAIT 3'b001
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`define DMA_WAIT 3'b001
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`define DMA_READ_REQ 3'b010
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`define DMA_READ_REQ 3'b010
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Line 170... |
wire [(AW-1):0] bus_nracks;
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wire [(AW-1):0] bus_nracks;
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assign bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };
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assign bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };
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reg last_read_request, last_read_ack,
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reg last_read_request, last_read_ack,
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last_write_request, last_write_ack;
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last_write_request, last_write_ack;
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reg trigger, abort;
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reg trigger, abort, user_halt;
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initial dma_state = `DMA_IDLE;
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initial dma_state = `DMA_IDLE;
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initial o_interrupt = 1'b0;
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initial o_interrupt = 1'b0;
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initial cfg_len = {(AW){1'b0}};
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initial cfg_len = {(AW){1'b0}};
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initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
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initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
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Line 195... |
// and thus to start.
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// and thus to start.
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if ((i_swb_stb)&&(i_swb_we))
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if ((i_swb_stb)&&(i_swb_we))
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begin
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begin
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case(i_swb_addr)
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case(i_swb_addr)
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2'b00: begin
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2'b00: begin
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if ((i_swb_data[27:16] == 12'hfed)
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if ((i_swb_data[31:16] == 16'h0fed)
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&&(cfg_len_nonzero))
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&&(cfg_len_nonzero))
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dma_state <= `DMA_WAIT;
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dma_state <= `DMA_WAIT;
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cfg_blocklen_sub_one
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cfg_blocklen_sub_one
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<= i_swb_data[(LGMEMLEN-1):0]
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<= i_swb_data[(LGMEMLEN-1):0]
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+ {(LGMEMLEN){1'b1}};
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+ {(LGMEMLEN){1'b1}};
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Line 223... |
nwacks <= 0;
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nwacks <= 0;
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nwritten <= 0;
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nwritten <= 0;
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nread <= 0;
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nread <= 0;
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if (abort)
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if (abort)
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dma_state <= `DMA_IDLE;
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dma_state <= `DMA_IDLE;
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else if (user_halt)
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dma_state <= `DMA_IDLE;
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else if (trigger)
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else if (trigger)
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dma_state <= `DMA_READ_REQ;
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dma_state <= `DMA_READ_REQ;
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end
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end
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`DMA_READ_REQ: begin
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`DMA_READ_REQ: begin
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nwritten <= 0;
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nwritten <= 0;
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Line 244... |
if (cfg_incs)
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if (cfg_incs)
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o_mwb_addr <= o_mwb_addr
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o_mwb_addr <= o_mwb_addr
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+ {{(AW-1){1'b0}},1'b1};
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+ {{(AW-1){1'b0}},1'b1};
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end
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end
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if (user_halt)
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dma_state <= `DMA_READ_ACK;
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if (i_mwb_err)
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if (i_mwb_err)
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begin
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begin
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cfg_len <= 0;
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cfg_len <= 0;
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dma_state <= `DMA_IDLE;
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dma_state <= `DMA_IDLE;
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end
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end
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if (abort)
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if (abort)
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dma_state <= `DMA_IDLE;
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dma_state <= `DMA_IDLE;
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if (i_mwb_ack)
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if (i_mwb_ack)
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begin
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begin
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nread <= nread+1;
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nread <= nread+1;
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end else if (i_mwb_ack)
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end else if (i_mwb_ack)
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begin
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begin
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nread <= nread+1;
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nread <= nread+1;
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if (last_read_ack) // (nread+1 == nracks)
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if (last_read_ack) // (nread+1 == nracks)
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dma_state <= `DMA_PRE_WRITE;
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dma_state <= `DMA_PRE_WRITE;
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if (user_halt)
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dma_state <= `DMA_IDLE;
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if (cfg_incs)
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if (cfg_incs)
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cfg_raddr <= cfg_raddr
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cfg_raddr <= cfg_raddr
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+ {{(AW-1){1'b0}},1'b1};
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+ {{(AW-1){1'b0}},1'b1};
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end
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end
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if (abort)
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if (abort)
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Line 312... |
if (i_mwb_ack)
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if (i_mwb_ack)
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begin
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begin
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nwacks <= nwacks+1;
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nwacks <= nwacks+1;
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cfg_len <= cfg_len +{(AW){1'b1}}; // -1
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cfg_len <= cfg_len +{(AW){1'b1}}; // -1
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end
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end
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if (user_halt)
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dma_state <= `DMA_WRITE_ACK;
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if (abort)
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if (abort)
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dma_state <= `DMA_IDLE;
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dma_state <= `DMA_IDLE;
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end
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end
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`DMA_WRITE_ACK: begin
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`DMA_WRITE_ACK: begin
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if (i_mwb_err)
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if (i_mwb_err)
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Line 343... |
dma_state <= `DMA_IDLE;
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dma_state <= `DMA_IDLE;
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endcase
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endcase
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initial o_interrupt = 1'b0;
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initial o_interrupt = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_interrupt <= (dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack)
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o_interrupt <= ((dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack)
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&&(last_write_ack)
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&&(last_write_ack)
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&&(cfg_len == {{(AW-1){1'b0}},1'b1});
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&&(cfg_len == {{(AW-1){1'b0}},1'b1}))
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||((dma_state != `DMA_IDLE)&&(i_mwb_err));
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initial cfg_err = 1'b0;
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initial cfg_err = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dma_state == `DMA_IDLE)
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if (dma_state == `DMA_IDLE)
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begin
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begin
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Line 478... |
always @(posedge i_clk)
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always @(posedge i_clk)
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abort <= (i_rst)||((i_swb_stb)&&(i_swb_we)
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abort <= (i_rst)||((i_swb_stb)&&(i_swb_we)
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&&(i_swb_addr == 2'b00)
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&&(i_swb_addr == 2'b00)
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&&(i_swb_data == 32'hffed0000));
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&&(i_swb_data == 32'hffed0000));
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initial user_halt = 1'b0;
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always @(posedge i_clk)
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user_halt <= ((user_halt)&&(dma_state != `DMA_IDLE))
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||((i_swb_stb)&&(i_swb_we)&&(dma_state != `DMA_IDLE)
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&&(i_swb_addr == 2'b00)
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&&(i_swb_data == 32'hafed0000));
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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