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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Diff between revs 48 and 69

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Rev 48 Rev 69
Line 77... Line 77...
//              being used, then you can read how much has been read into that
//              being used, then you can read how much has been read into that
//              buffer by reading from bits 25..16 of this control/status
//              buffer by reading from bits 25..16 of this control/status
//              register.
//              register.
//
//
// Creator:     Dan Gisselquist
// Creator:     Dan Gisselquist
//              Gisselquist Tecnology, LLC
//              Gisselquist Technology, LLC
//
//
// Copyright:   2015
// Copyright:   2015
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
Line 109... Line 109...
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
                        o_swb_ack, o_swb_stall, o_swb_data,
                        o_swb_ack, o_swb_stall, o_swb_data,
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
                i_dev_ints,
                i_dev_ints,
                o_interrupt,
                o_interrupt);
                i_other_busmaster_requests_bus);
 
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
        input                   i_clk;
        input                   i_clk;
        // Slave/control wishbone inputs
        // Slave/control wishbone inputs
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
Line 135... Line 134...
        // The interrupt device interrupt lines
        // The interrupt device interrupt lines
        input   [(DW-1):0]       i_dev_ints;
        input   [(DW-1):0]       i_dev_ints;
        // An interrupt to be set upon completion
        // An interrupt to be set upon completion
        output  reg             o_interrupt;
        output  reg             o_interrupt;
        // Need to release the bus for a higher priority user
        // Need to release the bus for a higher priority user
        input                   i_other_busmaster_requests_bus;
        //      This logic had lots of problems, so it is being
 
        //      removed.  If you want to make sure the bus is available
 
        //      for a higher priority user, adjust the transfer length
 
        //      accordingly.
 
        //
 
        // input                        i_other_busmaster_requests_bus;
 
        //
 
 
 
 
        reg                     cfg_wp; // Write protect
        reg                     cfg_wp; // Write protect
        reg                     cfg_err;
        reg                     cfg_err;
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
Line 167... Line 172...
                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
                begin
                begin
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                        begin
                        begin
                                nwritten <= nwritten+1;
                                nwritten <= nwritten+1;
                                if ((nwritten == nread-1)
                                if (nwritten == nread-1)
                                        ||(i_other_busmaster_requests_bus))
 
                                        // Wishbone interruptus
                                        // Wishbone interruptus
                                        o_mwb_stb <= 1'b0;
                                        o_mwb_stb <= 1'b0;
                                else if (cfg_incd) begin
                                else if (cfg_incd) begin
                                        o_mwb_addr <= o_mwb_addr + 1;
                                        o_mwb_addr <= o_mwb_addr + 1;
                                        cfg_waddr  <= cfg_waddr  + 1;
                                        cfg_waddr  <= cfg_waddr  + 1;
Line 203... Line 207...
                begin
                begin
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                        begin
                        begin
                                nacks <= nacks+1;
                                nacks <= nacks+1;
                                if ((nacks == {1'b0, cfg_blocklen_sub_one})
                                if ((nacks == {1'b0, cfg_blocklen_sub_one})
                                        ||(bus_nacks <= cfg_len-1)
                                        ||(bus_nacks <= cfg_len-1))
                                        ||(i_other_busmaster_requests_bus))
 
                                        // Wishbone interruptus
                                        // Wishbone interruptus
                                        o_mwb_stb <= 1'b0;
                                        o_mwb_stb <= 1'b0;
                                else if (cfg_incs) begin
                                else if (cfg_incs) begin
                                        o_mwb_addr <= o_mwb_addr + 1;
                                        o_mwb_addr <= o_mwb_addr + 1;
                                end
                                end

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