| Line 77... |
Line 77... |
// being used, then you can read how much has been read into that
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// being used, then you can read how much has been read into that
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// buffer by reading from bits 25..16 of this control/status
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// buffer by reading from bits 25..16 of this control/status
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// register.
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// register.
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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// Copyright: 2015
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// Copyright: 2015
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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| Line 109... |
Line 109... |
i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
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i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
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o_swb_ack, o_swb_stall, o_swb_data,
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o_swb_ack, o_swb_stall, o_swb_data,
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o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
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o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
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i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
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i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
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i_dev_ints,
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i_dev_ints,
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o_interrupt,
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o_interrupt);
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i_other_busmaster_requests_bus);
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parameter ADDRESS_WIDTH=32, LGMEMLEN = 10,
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parameter ADDRESS_WIDTH=32, LGMEMLEN = 10,
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DW=32, LGDV=5,AW=ADDRESS_WIDTH;
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DW=32, LGDV=5,AW=ADDRESS_WIDTH;
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input i_clk;
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input i_clk;
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// Slave/control wishbone inputs
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// Slave/control wishbone inputs
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input i_swb_cyc, i_swb_stb, i_swb_we;
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input i_swb_cyc, i_swb_stb, i_swb_we;
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| Line 135... |
Line 134... |
// The interrupt device interrupt lines
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// The interrupt device interrupt lines
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input [(DW-1):0] i_dev_ints;
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input [(DW-1):0] i_dev_ints;
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// An interrupt to be set upon completion
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// An interrupt to be set upon completion
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output reg o_interrupt;
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output reg o_interrupt;
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// Need to release the bus for a higher priority user
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// Need to release the bus for a higher priority user
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input i_other_busmaster_requests_bus;
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// This logic had lots of problems, so it is being
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// removed. If you want to make sure the bus is available
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// for a higher priority user, adjust the transfer length
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// accordingly.
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//
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// input i_other_busmaster_requests_bus;
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//
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reg cfg_wp; // Write protect
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reg cfg_wp; // Write protect
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reg cfg_err;
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reg cfg_err;
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reg [(AW-1):0] cfg_waddr, cfg_raddr, cfg_len;
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reg [(AW-1):0] cfg_waddr, cfg_raddr, cfg_len;
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| Line 167... |
Line 172... |
if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
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if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
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begin
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begin
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if ((o_mwb_stb)&&(~i_mwb_stall))
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if ((o_mwb_stb)&&(~i_mwb_stall))
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begin
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begin
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nwritten <= nwritten+1;
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nwritten <= nwritten+1;
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if ((nwritten == nread-1)
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if (nwritten == nread-1)
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||(i_other_busmaster_requests_bus))
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// Wishbone interruptus
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// Wishbone interruptus
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o_mwb_stb <= 1'b0;
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o_mwb_stb <= 1'b0;
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else if (cfg_incd) begin
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else if (cfg_incd) begin
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o_mwb_addr <= o_mwb_addr + 1;
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o_mwb_addr <= o_mwb_addr + 1;
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cfg_waddr <= cfg_waddr + 1;
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cfg_waddr <= cfg_waddr + 1;
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| Line 203... |
Line 207... |
begin
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begin
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if ((o_mwb_stb)&&(~i_mwb_stall))
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if ((o_mwb_stb)&&(~i_mwb_stall))
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begin
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begin
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nacks <= nacks+1;
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nacks <= nacks+1;
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if ((nacks == {1'b0, cfg_blocklen_sub_one})
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if ((nacks == {1'b0, cfg_blocklen_sub_one})
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||(bus_nacks <= cfg_len-1)
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||(bus_nacks <= cfg_len-1))
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||(i_other_busmaster_requests_bus))
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// Wishbone interruptus
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// Wishbone interruptus
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o_mwb_stb <= 1'b0;
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o_mwb_stb <= 1'b0;
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else if (cfg_incs) begin
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else if (cfg_incs) begin
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o_mwb_addr <= o_mwb_addr + 1;
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o_mwb_addr <= o_mwb_addr + 1;
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end
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end
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