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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipcounter.v] - Diff between revs 160 and 181
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| Rev 160 |
Rev 181 |
| Line 62... |
Line 62... |
output reg o_int;
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output reg o_int;
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initial o_int = 0;
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initial o_int = 0;
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initial o_wb_data = 32'h00;
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initial o_wb_data = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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if ((i_wb_stb)&&(i_wb_we))
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{ o_int, o_wb_data } <= { 1'b0, i_wb_data };
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{ o_int, o_wb_data } <= { 1'b0, i_wb_data };
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else if (i_ce)
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else if (i_ce)
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{ o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1};
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{ o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1};
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else
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else
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o_int <= 1'b0;
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o_int <= 1'b0;
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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endmodule
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endmodule
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