| Line 39... |
Line 39... |
i_ext_int,
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i_ext_int,
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// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
|
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data
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o_zip_debug);
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`ifdef DEBUG_SCOPE
|
|
, o_zip_debug
|
|
`endif
|
|
);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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LGICACHE=6, START_HALTED=1,
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LGICACHE=6, START_HALTED=1,
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AW=ADDRESS_WIDTH;
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AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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| Line 63... |
Line 66... |
input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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output reg o_dbg_ack;
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output reg o_dbg_ack;
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output wire o_dbg_stall;
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output wire o_dbg_stall;
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output wire [31:0] o_dbg_data;
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output wire [31:0] o_dbg_data;
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//
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//
|
|
`ifdef DEBUG_SCOPE
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output wire [31:0] o_zip_debug;
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output wire [31:0] o_zip_debug;
|
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`endif
|
|
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//
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//
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//
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//
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//
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//
|
wire sys_cyc, sys_stb, sys_we;
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wire sys_cyc, sys_stb, sys_we;
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| Line 163... |
Line 168... |
cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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o_wb_cyc, o_wb_stb,
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o_wb_cyc, o_wb_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_err,
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(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
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cpu_op_stall, cpu_pf_stall, cpu_i_count,
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cpu_op_stall, cpu_pf_stall, cpu_i_count
|
o_zip_debug);
|
`ifdef DEBUG_SCOPE
|
|
, o_zip_debug
|
|
`endif
|
|
);
|
|
|
// Return debug response values
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// Return debug response values
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assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
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assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
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initial o_dbg_ack = 1'b0;
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initial o_dbg_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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