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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 66 and 69

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Rev 66 Rev 69
Line 7... Line 7...
// Purpose:     In the spirit of keeping the Zip CPU small, this implements a
// Purpose:     In the spirit of keeping the Zip CPU small, this implements a
//              Zip System with no peripherals: Any peripherals you wish will
//              Zip System with no peripherals: Any peripherals you wish will
//              need to be implemented off-module.
//              need to be implemented off-module.
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
Line 45... Line 45...
`ifdef  DEBUG_SCOPE
`ifdef  DEBUG_SCOPE
                , o_zip_debug
                , o_zip_debug
`endif
`endif
                );
                );
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
                        LGICACHE=6, START_HALTED=1,
                        LGICACHE=6, START_HALTED=0,
                        AW=ADDRESS_WIDTH;
                        AW=ADDRESS_WIDTH;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [(AW-1):0]       o_wb_addr;
Line 102... Line 102...
        //
        //
        initial cmd_reset = 1'b1;
        initial cmd_reset = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
                cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
        //
        //
        initial cmd_halt  = 1'b1;
        initial cmd_halt  = START_HALTED;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
                else if (dbg_cmd_write)
                else if (dbg_cmd_write)
                        cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
                        cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));

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