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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 69 and 91

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Rev 69 Rev 91
Line 98... Line 98...
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg     [4:0]    cmd_addr;
        reg     [4:0]    cmd_addr;
        wire    [3:0]    cpu_dbg_cc;
        wire    [3:0]    cpu_dbg_cc;
        assign  dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
        assign  dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
        //
        //
 
        // Always start us off with an initial reset
 
        //
        initial cmd_reset = 1'b1;
        initial cmd_reset = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
                cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
        //
        //
        initial cmd_halt  = START_HALTED;
        initial cmd_halt  = START_HALTED;
Line 111... Line 113...
                else if (dbg_cmd_write)
                else if (dbg_cmd_write)
                        cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
                        cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
                else if ((cmd_step)||(cpu_break))
                else if ((cmd_step)||(cpu_break))
                        cmd_halt  <= 1'b1;
                        cmd_halt  <= 1'b1;
 
 
 
        initial cmd_clear_pf_cache = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        cmd_clear_pf_cache <= 1'b0;
                        cmd_clear_pf_cache <= 1'b0;
                else if (dbg_cmd_write)
                else if (dbg_cmd_write)
                        cmd_clear_pf_cache <= i_dbg_data[11];
                        cmd_clear_pf_cache <= i_dbg_data[11];
Line 123... Line 126...
        //
        //
        initial cmd_step  = 1'b0;
        initial cmd_step  = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]);
                cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]);
        //
        //
 
        initial cmd_addr = 5'h0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dbg_cmd_write)
                if (dbg_cmd_write)
                        cmd_addr <= i_dbg_data[4:0];
                        cmd_addr <= i_dbg_data[4:0];
 
 
        wire    cpu_reset;
        wire    cpu_reset;

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