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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Diff between revs 18 and 25

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Rev 18 Rev 25
Line 100... Line 100...
`define JIFFIES         4'h7    // Sets IVEC[1]
`define JIFFIES         4'h7    // Sets IVEC[1]
 
 
`define MSTR_TASK_CTR   4'h8
`define MSTR_TASK_CTR   4'h8
`define MSTR_MSTL_CTR   4'h9
`define MSTR_MSTL_CTR   4'h9
`define MSTR_PSTL_CTR   4'ha
`define MSTR_PSTL_CTR   4'ha
`define MSTR_ASTL_CTR   4'hb
`define MSTR_INST_CTR   4'hb
`define USER_TASK_CTR   4'hc
`define USER_TASK_CTR   4'hc
`define USER_MSTL_CTR   4'hd
`define USER_MSTL_CTR   4'hd
`define USER_PSTL_CTR   4'he
`define USER_PSTL_CTR   4'he
`define USER_ASTL_CTR   4'hf
`define USER_INST_CTR   4'hf
 
 
`define CACHEBASE       16'hc010        //
`define CACHEBASE       16'hc010        //
// `define      RTC_CLOCK       32'hc0000008    // A global something
// `define      RTC_CLOCK       32'hc0000008    // A global something
// `define      BITREV          32'hc0000003
// `define      BITREV          32'hc0000003
//
//
Line 199... Line 199...
        // register.
        // register.
        //
        //
        wire            cpu_break, dbg_cmd_write;
        wire            cpu_break, dbg_cmd_write;
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
        reg     [5:0]    cmd_addr;
        reg     [5:0]    cmd_addr;
        wire    [3:0]    cpu_dbg_cc;
        wire    [1:0]    cpu_dbg_cc;
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
        //
        //
        initial cmd_reset = 1'b1;
        initial cmd_reset = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
Line 248... Line 248...
        //      0x00200 -> cmd_stall
        //      0x00200 -> cmd_stall
        //      0x00400 -> cmd_halt
        //      0x00400 -> cmd_halt
        //      0x00800 -> cmd_clear_pf_cache
        //      0x00800 -> cmd_clear_pf_cache
        //      0x01000 -> cc.sleep
        //      0x01000 -> cc.sleep
        //      0x02000 -> cc.gie
        //      0x02000 -> cc.gie
        //      0x04000 -> cc.step
 
        //      0x08000 -> cc.break_en
 
        //      0x10000 -> External interrupt line is high
        //      0x10000 -> External interrupt line is high
        assign  cmd_data = { 15'h00, i_ext_int, cpu_dbg_cc,
        assign  cmd_data = { 15'h00, i_ext_int, 2'b00, cpu_dbg_cc,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        pic_data[15], cpu_reset, cmd_addr };
                        pic_data[15], cpu_reset, cmd_addr };
 
 
`ifdef  USE_TRAP
`ifdef  USE_TRAP
        //
        //
Line 336... Line 334...
 
 
        // Master Instruction counter
        // Master Instruction counter
        wire            mic_ack, mic_stall, mic_int;
        wire            mic_ack, mic_stall, mic_int;
        wire    [31:0]   mic_data;
        wire    [31:0]   mic_data;
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mic_ack, mic_stall, mic_data, mic_int);
                                mic_ack, mic_stall, mic_data, mic_int);
 
 
        //
        //
        // The user counters are different from those of the master.  They will
        // The user counters are different from those of the master.  They will
Line 372... Line 370...
 
 
        // User instruction counter
        // User instruction counter
        wire            uic_ack, uic_stall, uic_int;
        wire            uic_ack, uic_stall, uic_int;
        wire    [31:0]   uic_data;
        wire    [31:0]   uic_data;
        zipcounter      uins_ctr(i_clk,(cpu_i_count), sys_cyc,
        zipcounter      uins_ctr(i_clk,(cpu_i_count), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_ASTL_CTR),
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                uic_ack, uic_stall, uic_data, uic_int);
                                uic_ack, uic_stall, uic_data, uic_int);
 
 
        // A little bit of pre-cleanup (actr = accounting counters)
        // A little bit of pre-cleanup (actr = accounting counters)
        wire            actr_ack, actr_stall;
        wire            actr_ack, actr_stall;
Line 502... Line 500...
        initial dbg_ack = 1'b0;
        initial dbg_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
                                &&((cpu_cyc)||(~cpu_halt)||(cpu_dbg_stall));
                                &&((cpu_cyc)||((cmd_halt)&&(~cpu_halt))
 
                                        ||(cpu_dbg_stall));
 
 
        // Now for the external wishbone bus
        // Now for the external wishbone bus
        //      Need to arbitrate between the flash cache and the CPU
        //      Need to arbitrate between the flash cache and the CPU
        // The way this works, though, the CPU will stall once the flash 
        // The way this works, though, the CPU will stall once the flash 
        // cache gets access to the bus--the CPU will be stuck until the 
        // cache gets access to the bus--the CPU will be stuck until the 

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