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Line 80... |
// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// While I hate adding delays to any bus access, these two are required
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// to make timing close in my Basys-3 design.
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`define DELAY_EXT_BUS
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`define DELAY_DBG_BUS
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//
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//
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// Now, where am I placing all of my peripherals?
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`define PERIPHBASE 32'hc0000000
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`define PERIPHBASE 32'hc0000000
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`define INTCTRL 4'h0 //
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`define INTCTRL 4'h0 //
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`define WATCHDOG 4'h1 // Interrupt generates reset signal
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`define WATCHDOG 4'h1 // Interrupt generates reset signal
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`define CACHECTRL 4'h2 // Sets IVEC[0]
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`define CACHECTRL 4'h2 // Sets IVEC[0]
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`define CTRINT 4'h3 // Sets IVEC[5]
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`define CTRINT 4'h3 // Sets IVEC[5]
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Line 153... |
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// Delay the debug port by one clock, to meet timing requirements
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// Delay the debug port by one clock, to meet timing requirements
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wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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wire [31:0] dbg_idata, dbg_odata;
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wire [31:0] dbg_idata, dbg_odata;
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reg dbg_ack;
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reg dbg_ack;
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`ifdef DELAY_DBG_BUS
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busdelay #(1,32) wbdelay(i_clk,
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busdelay #(1,32) wbdelay(i_clk,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data,
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dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
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dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
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dbg_ack, dbg_stall, dbg_odata);
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dbg_ack, dbg_stall, dbg_odata);
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`else
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assign dbg_cyc = i_dbg_cyc;
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assign dbg_stb = i_dbg_stb;
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assign dbg_we = i_dbg_we;
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assign dbg_addr = i_dbg_addr;
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assign dbg_idata = i_dbg_data;
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assign o_dbg_ack = dbg_ack;
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assign o_dbg_stall = dbg_stall;
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assign o_dbg_data = dbg_odata;
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`endif
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//
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//
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//
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//
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//
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//
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wire sys_cyc, sys_stb, sys_we;
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wire sys_cyc, sys_stb, sys_we;
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Line 494... |
((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
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((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
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cpu_cyc, cpu_ext_ack, cpu_ext_stall,
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cpu_cyc, cpu_ext_ack, cpu_ext_stall,
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ext_addr, ext_odata, ext_we, ext_stb,
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ext_addr, ext_odata, ext_we, ext_stb,
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ext_cyc, ext_ack, ext_stall);
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ext_cyc, ext_ack, ext_stall);
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`ifdef DELAY_EXT_BUS
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busdelay #(32,32) extbus(i_clk,
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busdelay #(32,32) extbus(i_clk,
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ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
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ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
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ext_ack, ext_stall, ext_idata,
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ext_ack, ext_stall, ext_idata,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data);
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i_wb_ack, i_wb_stall, i_wb_data);
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`else
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assign o_wb_cyc = ext_cyc;
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assign o_wb_stb = ext_stb;
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assign o_wb_we = ext_we;
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assign o_wb_addr = ext_addr;
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assign o_wb_data = ext_odata;
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assign ext_ack = i_wb_ack;
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assign ext_stall = i_wb_stall;
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assign ext_idata = i_wb_data;
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`endif
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wire tmr_ack;
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wire tmr_ack;
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assign tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
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assign tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
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wire [31:0] tmr_data;
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wire [31:0] tmr_data;
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assign tmr_data = (tma_ack)?tma_data
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assign tmr_data = (tma_ack)?tma_data
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