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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Diff between revs 2 and 3

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Line 80... Line 80...
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
 
// While I hate adding delays to any bus access, these two are required
 
// to make timing close in my Basys-3 design.
 
`define DELAY_EXT_BUS
 
`define DELAY_DBG_BUS
 
//
 
//
 
// Now, where am I placing all of my peripherals?
`define PERIPHBASE      32'hc0000000
`define PERIPHBASE      32'hc0000000
`define INTCTRL         4'h0    // 
`define INTCTRL         4'h0    // 
`define WATCHDOG        4'h1    // Interrupt generates reset signal
`define WATCHDOG        4'h1    // Interrupt generates reset signal
`define CACHECTRL       4'h2    // Sets IVEC[0]
`define CACHECTRL       4'h2    // Sets IVEC[0]
`define CTRINT          4'h3    // Sets IVEC[5]
`define CTRINT          4'h3    // Sets IVEC[5]
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        // Delay the debug port by one clock, to meet timing requirements
        // Delay the debug port by one clock, to meet timing requirements
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
        wire    [31:0]   dbg_idata, dbg_odata;
        wire    [31:0]   dbg_idata, dbg_odata;
        reg             dbg_ack;
        reg             dbg_ack;
 
`ifdef  DELAY_DBG_BUS
        busdelay #(1,32) wbdelay(i_clk,
        busdelay #(1,32) wbdelay(i_clk,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
                        dbg_ack, dbg_stall, dbg_odata);
                        dbg_ack, dbg_stall, dbg_odata);
 
`else
 
        assign  dbg_cyc     = i_dbg_cyc;
 
        assign  dbg_stb     = i_dbg_stb;
 
        assign  dbg_we      = i_dbg_we;
 
        assign  dbg_addr    = i_dbg_addr;
 
        assign  dbg_idata   = i_dbg_data;
 
        assign  o_dbg_ack   = dbg_ack;
 
        assign  o_dbg_stall = dbg_stall;
 
        assign  o_dbg_data  = dbg_odata;
 
`endif
 
 
        // 
        // 
        //
        //
        //
        //
        wire    sys_cyc, sys_stb, sys_we;
        wire    sys_cyc, sys_stb, sys_we;
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                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
                        ext_addr, ext_odata, ext_we, ext_stb,
                        ext_addr, ext_odata, ext_we, ext_stb,
                                ext_cyc, ext_ack, ext_stall);
                                ext_cyc, ext_ack, ext_stall);
 
 
 
`ifdef  DELAY_EXT_BUS
        busdelay #(32,32) extbus(i_clk,
        busdelay #(32,32) extbus(i_clk,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                                ext_ack, ext_stall, ext_idata,
                                ext_ack, ext_stall, ext_idata,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                                i_wb_ack, i_wb_stall, i_wb_data);
                                i_wb_ack, i_wb_stall, i_wb_data);
 
`else
 
        assign  o_wb_cyc   = ext_cyc;
 
        assign  o_wb_stb   = ext_stb;
 
        assign  o_wb_we    = ext_we;
 
        assign  o_wb_addr  = ext_addr;
 
        assign  o_wb_data  = ext_odata;
 
        assign  ext_ack    = i_wb_ack;
 
        assign  ext_stall  = i_wb_stall;
 
        assign  ext_idata  = i_wb_data;
 
`endif
 
 
        wire            tmr_ack;
        wire            tmr_ack;
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
        wire    [31:0]   tmr_data;
        wire    [31:0]   tmr_data;
        assign  tmr_data = (tma_ack)?tma_data
        assign  tmr_data = (tma_ack)?tma_data

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