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///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
// Filename:    zipsystem.v
// Filename:    zipsystem.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     This portion of the ZIP CPU implements a number of soft
// Purpose:     This portion of the ZIP CPU implements a number of soft
//              peripherals to the CPU nearby its CORE.  The functionality
//              peripherals to the CPU nearby its CORE.  The functionality
//              sits on the data bus, and does not include any true
//              sits on the data bus, and does not include any true
//              external hardware peripherals.  The peripherals included here
//              external hardware peripherals.  The peripherals included here
//              include:
//              include:
//
//
//
//
//      Local interrupt controller--for any/all of the interrupts generated
//      Local interrupt controller--for any/all of the interrupts generated
//              here.  This would include a pin for interrupts generated
//              here.  This would include a pin for interrupts generated
//              elsewhere, so this interrupt controller could be a master
//              elsewhere, so this interrupt controller could be a master
//              handling all interrupts.  My interrupt controller would work
//              handling all interrupts.  My interrupt controller would work
//              for this purpose.
//              for this purpose.
//
//
//              The ZIP-CPU supports only one interrupt because, as I understand
//              The ZIP-CPU supports only one interrupt because, as I understand
//              modern systems (Linux), they tend to send all interrupts to the
//              modern systems (Linux), they tend to send all interrupts to the
//              same interrupt vector anyway.  Hence, that's what we do here.
//              same interrupt vector anyway.  Hence, that's what we do here.
//
//
//      Bus Error interrupts -- generates an interrupt any time the wishbone
//      Bus Error interrupts -- generates an interrupt any time the wishbone
//              bus produces an error on a given access, for whatever purpose
//              bus produces an error on a given access, for whatever purpose
//              also records the address on the bus at the time of the error.
//              also records the address on the bus at the time of the error.
//
//
//      Trap instructions
//      Trap instructions
//              Writing to this "register" will always create an interrupt.
//              Writing to this "register" will always create an interrupt.
//              After the interrupt, this register may be read to see what
//              After the interrupt, this register may be read to see what
//              value had been written to it.
//              value had been written to it.
//
//
//      Bit reverse register ... ?
//      Bit reverse register ... ?
//
//
//      (Potentially an eventual floating point co-processor ...)
//      (Potentially an eventual floating point co-processor ...)
//
//
//      Real-time clock
//      Real-time clock
//
//
//      Interval timer(s) (Count down from fixed value, and either stop on
//      Interval timer(s) (Count down from fixed value, and either stop on
//              zero, or issue an interrupt and restart automatically on zero)
//              zero, or issue an interrupt and restart automatically on zero)
//              These can be implemented as watchdog timers if desired--the
//              These can be implemented as watchdog timers if desired--the
//              only difference is that a watchdog timer's interrupt feeds the
//              only difference is that a watchdog timer's interrupt feeds the
//              reset line instead of the processor interrupt line.
//              reset line instead of the processor interrupt line.
//
//
//      Watch-dog timer: this is the same as an interval timer, only it's
//      Watch-dog timer: this is the same as an interval timer, only it's
//              interrupt/time-out line is wired to the reset line instead of
//              interrupt/time-out line is wired to the reset line instead of
//              the interrupt line of the CPU.
//              the interrupt line of the CPU.
//
//
//      ROM Memory map
//      ROM Memory map
//              Set a register to control this map, and a DMA will begin to
//              Set a register to control this map, and a DMA will begin to
//              fill this memory from a slower FLASH.  Once filled, accesses
//              fill this memory from a slower FLASH.  Once filled, accesses
//              will be from this memory instead of 
//              will be from this memory instead of 
//
//
//
//
//      Doing some market comparison, let's look at what peripherals a TI
//      Doing some market comparison, let's look at what peripherals a TI
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
//      watchdog-timers,
//      watchdog-timers,
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
//
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
 
// While I hate adding delays to any bus access, these two are required
 
// to make timing close in my Basys-3 design.
 
`define DELAY_EXT_BUS
 
`define DELAY_DBG_BUS
 
//
 
//
 
// Now, where am I placing all of my peripherals?
`define PERIPHBASE      32'hc0000000
`define PERIPHBASE      32'hc0000000
`define INTCTRL         4'h0    // 
`define INTCTRL         4'h0    // 
`define WATCHDOG        4'h1    // Interrupt generates reset signal
`define WATCHDOG        4'h1    // Interrupt generates reset signal
`define CACHECTRL       4'h2    // Sets IVEC[0]
`define CACHECTRL       4'h2    // Sets IVEC[0]
`define CTRINT          4'h3    // Sets IVEC[5]
`define CTRINT          4'h3    // Sets IVEC[5]
`define TIMER_A         4'h4    // Sets IVEC[4]
`define TIMER_A         4'h4    // Sets IVEC[4]
`define TIMER_B         4'h5    // Sets IVEC[3]
`define TIMER_B         4'h5    // Sets IVEC[3]
`define TIMER_C         4'h6    // Sets IVEC[2]
`define TIMER_C         4'h6    // Sets IVEC[2]
`define JIFFIES         4'h7    // Sets IVEC[1]
`define JIFFIES         4'h7    // Sets IVEC[1]
 
 
`define MSTR_TASK_CTR   4'h8
`define MSTR_TASK_CTR   4'h8
`define MSTR_MSTL_CTR   4'h9
`define MSTR_MSTL_CTR   4'h9
`define MSTR_PSTL_CTR   4'ha
`define MSTR_PSTL_CTR   4'ha
`define MSTR_ASTL_CTR   4'hb
`define MSTR_ASTL_CTR   4'hb
`define USER_TASK_CTR   4'hc
`define USER_TASK_CTR   4'hc
`define USER_MSTL_CTR   4'hd
`define USER_MSTL_CTR   4'hd
`define USER_PSTL_CTR   4'he
`define USER_PSTL_CTR   4'he
`define USER_ASTL_CTR   4'hf
`define USER_ASTL_CTR   4'hf
 
 
`define CACHEBASE       16'hc010        //
`define CACHEBASE       16'hc010        //
// `define      RTC_CLOCK       32'hc0000008    // A global something
// `define      RTC_CLOCK       32'hc0000008    // A global something
// `define      BITREV          32'hc0000003
// `define      BITREV          32'hc0000003
//
//
//      DBGCTRL
//      DBGCTRL
//              10 HALT
//              10 HALT
//               9 HALT(ED)
//               9 HALT(ED)
//               8 STEP (W=1 steps, and returns to halted)
//               8 STEP (W=1 steps, and returns to halted)
//               7 INTERRUPT-FLAG
//               7 INTERRUPT-FLAG
//               6 RESET_FLAG
//               6 RESET_FLAG
//              ADDRESS:
//              ADDRESS:
//               5      PERIPHERAL-BIT
//               5      PERIPHERAL-BIT
//              [4:0]   REGISTER-ADDR
//              [4:0]   REGISTER-ADDR
//      DBGDATA
//      DBGDATA
//              read/writes internal registers
//              read/writes internal registers
module  zipsystem(i_clk, i_rst,
module  zipsystem(i_clk, i_rst,
                // Wishbone master interface from the CPU
                // Wishbone master interface from the CPU
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data,
                // Incoming interrupts
                // Incoming interrupts
                i_ext_int,
                i_ext_int,
                // Wishbone slave interface for debugging purposes
                // Wishbone slave interface for debugging purposes
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
        parameter       RESET_ADDRESS=32'h0100000;
        parameter       RESET_ADDRESS=32'h0100000;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [31:0]   o_wb_addr;
        output  wire    [31:0]   o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        // Incoming interrupts
        // Incoming interrupts
        input                   i_ext_int;
        input                   i_ext_int;
        // Wishbone slave
        // Wishbone slave
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
        output  wire            o_dbg_ack;
        output  wire            o_dbg_ack;
        output  wire            o_dbg_stall;
        output  wire            o_dbg_stall;
        output  wire    [31:0]   o_dbg_data;
        output  wire    [31:0]   o_dbg_data;
 
 
        wire    [31:0]   ext_idata;
        wire    [31:0]   ext_idata;
 
 
        // Delay the debug port by one clock, to meet timing requirements
        // Delay the debug port by one clock, to meet timing requirements
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
        wire    [31:0]   dbg_idata, dbg_odata;
        wire    [31:0]   dbg_idata, dbg_odata;
        reg             dbg_ack;
        reg             dbg_ack;
 
`ifdef  DELAY_DBG_BUS
        busdelay #(1,32) wbdelay(i_clk,
        busdelay #(1,32) wbdelay(i_clk,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
                        dbg_ack, dbg_stall, dbg_odata);
                        dbg_ack, dbg_stall, dbg_odata);
 
`else
 
        assign  dbg_cyc     = i_dbg_cyc;
 
        assign  dbg_stb     = i_dbg_stb;
 
        assign  dbg_we      = i_dbg_we;
 
        assign  dbg_addr    = i_dbg_addr;
 
        assign  dbg_idata   = i_dbg_data;
 
        assign  o_dbg_ack   = dbg_ack;
 
        assign  o_dbg_stall = dbg_stall;
 
        assign  o_dbg_data  = dbg_odata;
 
`endif
 
 
        // 
        // 
        //
        //
        //
        //
        wire    sys_cyc, sys_stb, sys_we;
        wire    sys_cyc, sys_stb, sys_we;
        wire    [3:0]    sys_addr;
        wire    [3:0]    sys_addr;
        wire    [31:0]   cpu_addr;
        wire    [31:0]   cpu_addr;
        wire    [31:0]   sys_data;
        wire    [31:0]   sys_data;
        // wire         sys_ack, sys_stall;
        // wire         sys_ack, sys_stall;
 
 
        //
        //
        // The external debug interface
        // The external debug interface
        //
        //
        // We offer only a limited interface here, requiring a pre-register
        // We offer only a limited interface here, requiring a pre-register
        // write to set the local address.  This interface allows access to
        // write to set the local address.  This interface allows access to
        // the Zip System on a debug basis only, and not to the rest of the
        // the Zip System on a debug basis only, and not to the rest of the
        // wishbone bus.  Further, to access these registers, the control
        // wishbone bus.  Further, to access these registers, the control
        // register must first be accessed to both stop the CPU and to 
        // register must first be accessed to both stop the CPU and to 
        // set the following address in question.  Hence all accesses require
        // set the following address in question.  Hence all accesses require
        // two accesses: write the address to the control register (and halt
        // two accesses: write the address to the control register (and halt
        // the CPU if not halted), then read/write the data from the data
        // the CPU if not halted), then read/write the data from the data
        // register.
        // register.
        //
        //
        wire            cpu_break;
        wire            cpu_break;
        reg             cmd_reset, cmd_halt, cmd_step;
        reg             cmd_reset, cmd_halt, cmd_step;
        reg     [5:0]    cmd_addr;
        reg     [5:0]    cmd_addr;
        initial cmd_reset = 1'b1;
        initial cmd_reset = 1'b1;
        initial cmd_halt  = 1'b1;
        initial cmd_halt  = 1'b1;
        initial cmd_step  = 1'b0;
        initial cmd_step  = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        cmd_halt <= 1'b0;
                        cmd_halt <= 1'b0;
                        cmd_step <= 1'b0;
                        cmd_step <= 1'b0;
                        cmd_reset<= 1'b0;
                        cmd_reset<= 1'b0;
                        cmd_addr <= 6'h00;
                        cmd_addr <= 6'h00;
                end else if ((dbg_cyc)&&(dbg_stb)
                end else if ((dbg_cyc)&&(dbg_stb)
                                        &&(dbg_we)&&(~dbg_addr))
                                        &&(dbg_we)&&(~dbg_addr))
                begin
                begin
                        cmd_halt <= dbg_idata[10];
                        cmd_halt <= dbg_idata[10];
                        cmd_step <= dbg_idata[ 8];
                        cmd_step <= dbg_idata[ 8];
                        cmd_reset<= dbg_idata[ 6];
                        cmd_reset<= dbg_idata[ 6];
                        cmd_addr <= dbg_idata[5:0];
                        cmd_addr <= dbg_idata[5:0];
                end else if (cmd_step)
                end else if (cmd_step)
                begin
                begin
                        cmd_halt <= 1'b1;
                        cmd_halt <= 1'b1;
                        cmd_step <= 1'b0;
                        cmd_step <= 1'b0;
                end else if (cpu_break)
                end else if (cpu_break)
                        cmd_halt <= 1'b1;
                        cmd_halt <= 1'b1;
        wire    cpu_reset;
        wire    cpu_reset;
        assign  cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
        assign  cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
 
 
        wire    cpu_halt, cpu_dbg_stall;
        wire    cpu_halt, cpu_dbg_stall;
        assign  cpu_halt = (cmd_halt)&&(~cmd_step);
        assign  cpu_halt = (cmd_halt)&&(~cmd_step);
        wire    [31:0]   pic_data;
        wire    [31:0]   pic_data;
        wire    [31:0]   cmd_data;
        wire    [31:0]   cmd_data;
        assign  cmd_data = { 21'h00, cmd_halt, (~cpu_dbg_stall), 1'b0, pic_data[15],
        assign  cmd_data = { 21'h00, cmd_halt, (~cpu_dbg_stall), 1'b0, pic_data[15],
                        cpu_reset, cmd_addr };
                        cpu_reset, cmd_addr };
 
 
`ifdef  USE_TRAP
`ifdef  USE_TRAP
        //
        //
        // The TRAP peripheral
        // The TRAP peripheral
        //
        //
        wire            trap_ack, trap_stall, trap_int;
        wire            trap_ack, trap_stall, trap_int;
        wire    [31:0]   trap_data;
        wire    [31:0]   trap_data;
        ziptrap trapp(i_clk,
        ziptrap trapp(i_clk,
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
                                sys_data,
                                sys_data,
                                trap_ack, trap_stall, trap_data, trap_int);
                                trap_ack, trap_stall, trap_data, trap_int);
`endif
`endif
 
 
        //
        //
        // The WATCHDOG Timer
        // The WATCHDOG Timer
        //
        //
        wire            wdt_ack, wdt_stall, wdt_reset;
        wire            wdt_ack, wdt_stall, wdt_reset;
        wire    [31:0]   wdt_data;
        wire    [31:0]   wdt_data;
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
                                sys_data,
                                sys_data,
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
 
 
        //
        //
        // The Flash Cache, a pre-read cache to memory that can be used to
        // The Flash Cache, a pre-read cache to memory that can be used to
        // create a fast memory access area
        // create a fast memory access area
        //
        //
        wire            cache_int;
        wire            cache_int;
        wire    [31:0]   cache_data;
        wire    [31:0]   cache_data;
        wire            cache_stb, cache_ack, cache_stall;
        wire            cache_stb, cache_ack, cache_stall;
        wire            fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;
        wire            fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;
        wire    [31:0]   fc_data, fc_addr;
        wire    [31:0]   fc_data, fc_addr;
        flashcache      #(10) manualcache(i_clk,
        flashcache      #(10) manualcache(i_clk,
                                sys_cyc, cache_stb,
                                sys_cyc, cache_stb,
                                ((sys_stb)&&(sys_addr == `CACHECTRL)),
                                ((sys_stb)&&(sys_addr == `CACHECTRL)),
                                sys_we, cpu_addr[9:0], sys_data,
                                sys_we, cpu_addr[9:0], sys_data,
                                        cache_ack, cache_stall, cache_data,
                                        cache_ack, cache_stall, cache_data,
                                // Need the outgoing CACHE wishbone bus
                                // Need the outgoing CACHE wishbone bus
                                fc_cyc, fc_stb, fc_we, fc_addr, fc_data,
                                fc_cyc, fc_stb, fc_we, fc_addr, fc_data,
                                        fc_ack, fc_stall, ext_idata,
                                        fc_ack, fc_stall, ext_idata,
                                // Cache interrupt, for upon completion
                                // Cache interrupt, for upon completion
                                cache_int);
                                cache_int);
 
 
 
 
        // Counters -- for performance measurement and accounting
        // Counters -- for performance measurement and accounting
        //
        //
        // Here's the stuff we'll be counting ....
        // Here's the stuff we'll be counting ....
        //
        //
        wire            cpu_mem_stall, cpu_pf_stall, cpu_alu_stall;
        wire            cpu_mem_stall, cpu_pf_stall, cpu_alu_stall;
 
 
        //
        //
        // The master counters will, in general, not be reset.  They'll be used
        // The master counters will, in general, not be reset.  They'll be used
        // for an overall counter.
        // for an overall counter.
        //
        //
        // Master task counter
        // Master task counter
        wire            mtc_ack, mtc_stall, mtc_int;
        wire            mtc_ack, mtc_stall, mtc_int;
        wire    [31:0]   mtc_data;
        wire    [31:0]   mtc_data;
        zipcounter      mtask_ctr(i_clk, (~cmd_halt), sys_cyc,
        zipcounter      mtask_ctr(i_clk, (~cmd_halt), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
 
 
        // Master Memory-Stall counter
        // Master Memory-Stall counter
        wire            mmc_ack, mmc_stall, mmc_int;
        wire            mmc_ack, mmc_stall, mmc_int;
        wire    [31:0]   mmc_data;
        wire    [31:0]   mmc_data;
        zipcounter      mmstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
        zipcounter      mmstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mmc_ack, mmc_stall, mmc_data, mmc_int);
                                mmc_ack, mmc_stall, mmc_data, mmc_int);
 
 
        // Master PreFetch-Stall counter
        // Master PreFetch-Stall counter
        wire            mpc_ack, mpc_stall, mpc_int;
        wire            mpc_ack, mpc_stall, mpc_int;
        wire    [31:0]   mpc_data;
        wire    [31:0]   mpc_data;
        zipcounter      mpstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
        zipcounter      mpstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
 
 
        // Master ALU-Stall counter
        // Master ALU-Stall counter
        wire            mac_ack, mac_stall, mac_int;
        wire            mac_ack, mac_stall, mac_int;
        wire    [31:0]   mac_data;
        wire    [31:0]   mac_data;
        zipcounter      mastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
        zipcounter      mastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),
                                (sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                mac_ack, mac_stall, mac_data, mac_int);
                                mac_ack, mac_stall, mac_data, mac_int);
 
 
        //
        //
        // The user counters are different from those of the master.  They will
        // The user counters are different from those of the master.  They will
        // be reset any time a task is given control of the CPU.
        // be reset any time a task is given control of the CPU.
        //
        //
        // User task counter
        // User task counter
        wire            utc_ack, utc_stall, utc_int;
        wire            utc_ack, utc_stall, utc_int;
        wire    [31:0]   utc_data;
        wire    [31:0]   utc_data;
        zipcounter      utask_ctr(i_clk,(~cmd_halt), sys_cyc,
        zipcounter      utask_ctr(i_clk,(~cmd_halt), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                utc_ack, utc_stall, utc_data, utc_int);
                                utc_ack, utc_stall, utc_data, utc_int);
 
 
        // User Memory-Stall counter
        // User Memory-Stall counter
        wire            umc_ack, umc_stall, umc_int;
        wire            umc_ack, umc_stall, umc_int;
        wire    [31:0]   umc_data;
        wire    [31:0]   umc_data;
        zipcounter      umstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
        zipcounter      umstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                umc_ack, umc_stall, umc_data, umc_int);
                                umc_ack, umc_stall, umc_data, umc_int);
 
 
        // User PreFetch-Stall counter
        // User PreFetch-Stall counter
        wire            upc_ack, upc_stall, upc_int;
        wire            upc_ack, upc_stall, upc_int;
        wire    [31:0]   upc_data;
        wire    [31:0]   upc_data;
        zipcounter      upstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
        zipcounter      upstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                upc_ack, upc_stall, upc_data, upc_int);
                                upc_ack, upc_stall, upc_data, upc_int);
 
 
        // User ALU-Stall counter
        // User ALU-Stall counter
        wire            uac_ack, uac_stall, uac_int;
        wire            uac_ack, uac_stall, uac_int;
        wire    [31:0]   uac_data;
        wire    [31:0]   uac_data;
        zipcounter      uastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
        zipcounter      uastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_ASTL_CTR),
                                (sys_stb)&&(sys_addr == `USER_ASTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                uac_ack, uac_stall, uac_data, uac_int);
                                uac_ack, uac_stall, uac_data, uac_int);
 
 
        // A little bit of pre-cleanup (actr = accounting counters)
        // A little bit of pre-cleanup (actr = accounting counters)
        wire            actr_ack, actr_stall;
        wire            actr_ack, actr_stall;
        wire    [31:0]   actr_data;
        wire    [31:0]   actr_data;
        assign  actr_ack = ((mtc_ack | mmc_ack | mpc_ack | mac_ack)
        assign  actr_ack = ((mtc_ack | mmc_ack | mpc_ack | mac_ack)
                                |(utc_ack | umc_ack | upc_ack | uac_ack));
                                |(utc_ack | umc_ack | upc_ack | uac_ack));
        assign  actr_stall = ((mtc_stall | mmc_stall | mpc_stall | mac_stall)
        assign  actr_stall = ((mtc_stall | mmc_stall | mpc_stall | mac_stall)
                                |(utc_stall | umc_stall | upc_stall|uac_stall));
                                |(utc_stall | umc_stall | upc_stall|uac_stall));
        assign  actr_data = ((mtc_ack) ? mtc_data
        assign  actr_data = ((mtc_ack) ? mtc_data
                                : ((mmc_ack) ? mmc_data
                                : ((mmc_ack) ? mmc_data
                                : ((mpc_ack) ? mpc_data
                                : ((mpc_ack) ? mpc_data
                                : ((mac_ack) ? mac_data
                                : ((mac_ack) ? mac_data
                                : ((utc_ack) ? utc_data
                                : ((utc_ack) ? utc_data
                                : ((umc_ack) ? umc_data
                                : ((umc_ack) ? umc_data
                                : ((upc_ack) ? upc_data
                                : ((upc_ack) ? upc_data
                                : uac_data)))))));
                                : uac_data)))))));
 
 
 
 
 
 
        //
        //
        // Counter Interrupt controller
        // Counter Interrupt controller
        //
        //
        reg             ctri_ack;
        reg             ctri_ack;
        wire            ctri_stall, ctri_int, ctri_sel;
        wire            ctri_stall, ctri_int, ctri_sel;
        wire    [7:0]    ctri_vector;
        wire    [7:0]    ctri_vector;
        wire    [31:0]   ctri_data;
        wire    [31:0]   ctri_data;
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
        assign  ctri_vector = { mtc_int, mmc_int, mpc_int, mac_int,
        assign  ctri_vector = { mtc_int, mmc_int, mpc_int, mac_int,
                                        utc_int, umc_int, upc_int, uac_int };
                                        utc_int, umc_int, upc_int, uac_int };
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
                                sys_data, ctri_data, ctri_vector, ctri_int);
                                sys_data, ctri_data, ctri_vector, ctri_int);
        always @(posedge i_clk)
        always @(posedge i_clk)
                ctri_ack <= ctri_sel;
                ctri_ack <= ctri_sel;
 
 
 
 
        //
        //
        // Timer A
        // Timer A
        //
        //
        wire            tma_ack, tma_stall, tma_int;
        wire            tma_ack, tma_stall, tma_int;
        wire    [31:0]   tma_data;
        wire    [31:0]   tma_data;
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
                                sys_data,
                                sys_data,
                        tma_ack, tma_stall, tma_data, tma_int);
                        tma_ack, tma_stall, tma_data, tma_int);
 
 
        //
        //
        // Timer B
        // Timer B
        //
        //
        wire            tmb_ack, tmb_stall, tmb_int;
        wire            tmb_ack, tmb_stall, tmb_int;
        wire    [31:0]   tmb_data;
        wire    [31:0]   tmb_data;
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
                                sys_data,
                                sys_data,
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
 
 
        //
        //
        // Timer C
        // Timer C
        //
        //
        wire            tmc_ack, tmc_stall, tmc_int;
        wire            tmc_ack, tmc_stall, tmc_int;
        wire    [31:0]   tmc_data;
        wire    [31:0]   tmc_data;
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
                                sys_data,
                                sys_data,
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
 
 
        //
        //
        // JIFFIES
        // JIFFIES
        //
        //
        wire            jif_ack, jif_stall, jif_int;
        wire            jif_ack, jif_stall, jif_int;
        wire    [31:0]   jif_data;
        wire    [31:0]   jif_data;
        zipjiffies jiffies(i_clk, ~cmd_halt,
        zipjiffies jiffies(i_clk, ~cmd_halt,
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
                                sys_data,
                                sys_data,
                        jif_ack, jif_stall, jif_data, jif_int);
                        jif_ack, jif_stall, jif_data, jif_int);
 
 
        //
        //
        // The programmable interrupt controller peripheral
        // The programmable interrupt controller peripheral
        //
        //
        wire            pic_interrupt;
        wire            pic_interrupt;
        wire    [6:0]    int_vector;
        wire    [6:0]    int_vector;
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
                                        jif_int, cache_int };
                                        jif_int, cache_int };
        icontrol #(7)   pic(i_clk, cpu_reset,
        icontrol #(7)   pic(i_clk, cpu_reset,
                                (sys_cyc)&&(sys_stb)&&(sys_we)
                                (sys_cyc)&&(sys_stb)&&(sys_we)
                                        &&(sys_addr==`INTCTRL),
                                        &&(sys_addr==`INTCTRL),
                                sys_data, pic_data,
                                sys_data, pic_data,
                                int_vector, pic_interrupt);
                                int_vector, pic_interrupt);
        reg     pic_ack;
        reg     pic_ack;
        always @(posedge i_clk)
        always @(posedge i_clk)
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
 
 
        //
        //
        // The CPU itself
        // The CPU itself
        //
        //
        wire            cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;
        wire            cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;
        wire    [31:0]   cpu_data, wb_data;
        wire    [31:0]   cpu_data, wb_data;
        wire            cpu_ack, cpu_stall;
        wire            cpu_ack, cpu_stall;
        wire    [31:0]   cpu_dbg_data;
        wire    [31:0]   cpu_dbg_data;
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
                                        &&(dbg_we)&&(dbg_addr));
                                        &&(dbg_we)&&(dbg_addr));
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
                        cpu_halt, cmd_addr[4:0], cpu_dbg_we,
                        cpu_halt, cmd_addr[4:0], cpu_dbg_we,
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
                                cpu_break,
                                cpu_break,
                        cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
                        cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
                                cpu_ack, cpu_stall, wb_data,
                                cpu_ack, cpu_stall, wb_data,
                        cpu_mem_stall, cpu_pf_stall, cpu_alu_stall);
                        cpu_mem_stall, cpu_pf_stall, cpu_alu_stall);
 
 
        // Now, arbitrate the bus ... first for the local peripherals
        // Now, arbitrate the bus ... first for the local peripherals
        assign  sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
        assign  sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
        assign  sys_stb = (cpu_cyc)
        assign  sys_stb = (cpu_cyc)
                                ? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))
                                ? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
 
 
        assign  sys_we  = (cpu_cyc) ? cpu_we : dbg_we;
        assign  sys_we  = (cpu_cyc) ? cpu_we : dbg_we;
        assign  sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];
        assign  sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];
        assign  sys_data= (cpu_cyc) ? cpu_data : dbg_idata;
        assign  sys_data= (cpu_cyc) ? cpu_data : dbg_idata;
        assign  cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));
        assign  cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));
 
 
        // Return debug response values
        // Return debug response values
        assign  dbg_odata = (~dbg_addr)?cmd_data
        assign  dbg_odata = (~dbg_addr)?cmd_data
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
        initial dbg_ack = 1'b0;
        initial dbg_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
                                &&((cpu_cyc)||(~cpu_halt)||(cpu_dbg_stall));
                                &&((cpu_cyc)||(~cpu_halt)||(cpu_dbg_stall));
 
 
        // Now for the external wishbone bus
        // Now for the external wishbone bus
        //      Need to arbitrate between the flash cache and the CPU
        //      Need to arbitrate between the flash cache and the CPU
        // The way this works, though, the CPU will stall once the flash 
        // The way this works, though, the CPU will stall once the flash 
        // cache gets access to the bus--the CPU will be stuck until the 
        // cache gets access to the bus--the CPU will be stuck until the 
        // flash cache is finished with the bus.
        // flash cache is finished with the bus.
        wire            ext_cyc, ext_stb, ext_we;
        wire            ext_cyc, ext_stb, ext_we;
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;
        wire    [31:0]   ext_addr, ext_odata;
        wire    [31:0]   ext_addr, ext_odata;
        wbarbiter #(32,32) flashvcpu(i_clk, i_rst,
        wbarbiter #(32,32) flashvcpu(i_clk, i_rst,
                        fc_addr, fc_data, fc_we, fc_stb, fc_cyc,
                        fc_addr, fc_data, fc_we, fc_stb, fc_cyc,
                                        fc_ack, fc_stall,
                                        fc_ack, fc_stall,
                        cpu_addr, cpu_data, cpu_we,
                        cpu_addr, cpu_data, cpu_we,
                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
                        ext_addr, ext_odata, ext_we, ext_stb,
                        ext_addr, ext_odata, ext_we, ext_stb,
                                ext_cyc, ext_ack, ext_stall);
                                ext_cyc, ext_ack, ext_stall);
 
 
 
`ifdef  DELAY_EXT_BUS
        busdelay #(32,32) extbus(i_clk,
        busdelay #(32,32) extbus(i_clk,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                                ext_ack, ext_stall, ext_idata,
                                ext_ack, ext_stall, ext_idata,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                                i_wb_ack, i_wb_stall, i_wb_data);
                                i_wb_ack, i_wb_stall, i_wb_data);
 
`else
 
        assign  o_wb_cyc   = ext_cyc;
 
        assign  o_wb_stb   = ext_stb;
 
        assign  o_wb_we    = ext_we;
 
        assign  o_wb_addr  = ext_addr;
 
        assign  o_wb_data  = ext_odata;
 
        assign  ext_ack    = i_wb_ack;
 
        assign  ext_stall  = i_wb_stall;
 
        assign  ext_idata  = i_wb_data;
 
`endif
 
 
        wire            tmr_ack;
        wire            tmr_ack;
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
        wire    [31:0]   tmr_data;
        wire    [31:0]   tmr_data;
        assign  tmr_data = (tma_ack)?tma_data
        assign  tmr_data = (tma_ack)?tma_data
                                :(tmb_ack ? tmb_data
                                :(tmb_ack ? tmb_data
                                :(tmc_ack ? tmc_data
                                :(tmc_ack ? tmc_data
                                :jif_data));
                                :jif_data));
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
                        :((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)
                        :((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
                        :(ext_idata)));
                        :(ext_idata)));
 
 
        assign  cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
        assign  cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
                                | wdt_stall | cache_stall
                                | wdt_stall | cache_stall
                                | cpu_ext_stall);
                                | cpu_ext_stall);
        assign  cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
        assign  cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
endmodule
endmodule
 
 

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