| Line 132... |
Line 132... |
// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data);
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o_dbg_ack, o_dbg_stall, o_dbg_data);
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parameter RESET_ADDRESS=32'h0100000;
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parameter RESET_ADDRESS=32'h0100000, START_HALTED=1,
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EXTERNAL_INTERRUPTS=1;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [31:0] o_wb_addr;
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output wire [31:0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Incoming interrupts
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// Incoming interrupts
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input i_ext_int;
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input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int;
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// Outgoing interrupt
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// Outgoing interrupt
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output wire o_ext_int;
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output wire o_ext_int;
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// Wishbone slave
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// Wishbone slave
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input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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| Line 209... |
Line 210... |
cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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//
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//
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initial cmd_halt = 1'b1;
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initial cmd_halt = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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cmd_halt <= 1'b1;
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cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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else if (dbg_cmd_write)
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else if (dbg_cmd_write)
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cmd_halt <= dbg_idata[10];
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cmd_halt <= dbg_idata[10];
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else if ((cmd_step)||(cpu_break))
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else if ((cmd_step)||(cpu_break))
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cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
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| Line 232... |
Line 233... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (dbg_cmd_write)
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if (dbg_cmd_write)
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cmd_addr <= dbg_idata[5:0];
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cmd_addr <= dbg_idata[5:0];
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wire cpu_reset;
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wire cpu_reset;
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assign cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
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assign cpu_reset = (cmd_reset)||(wdt_reset);
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wire cpu_halt, cpu_dbg_stall;
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wire cpu_halt, cpu_dbg_stall;
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assign cpu_halt = (cmd_halt)&&(~cmd_step);
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assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
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wire [31:0] pic_data;
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wire [31:0] pic_data;
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wire [31:0] cmd_data;
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wire [31:0] cmd_data;
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// Values:
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// Values:
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// 0x0003f -> cmd_addr mask
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// 0x0003f -> cmd_addr mask
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// 0x00040 -> reset
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// 0x00040 -> reset
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// 0x00080 -> interrrupts enabled
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// 0x00080 -> PIC interrrupts enabled
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// 0x00100 -> cmd_step
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// 0x00100 -> cmd_step
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// 0x00200 -> cmd_stall
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// 0x00200 -> cmd_stall
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// 0x00400 -> cmd_halt
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// 0x00400 -> cmd_halt
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// 0x00800 -> cmd_clear_pf_cache
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// 0x00800 -> cmd_clear_pf_cache
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// 0x01000 -> cc.sleep
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// 0x01000 -> cc.sleep
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// 0x02000 -> cc.gie
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// 0x02000 -> cc.gie
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// 0x10000 -> External interrupt line is high
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// 0x10000 -> External interrupt line is high
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assign cmd_data = { 15'h00, i_ext_int, 2'b00, cpu_dbg_cc,
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assign cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
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2'b00, cpu_dbg_cc,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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pic_data[15], cpu_reset, cmd_addr };
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pic_data[15], cpu_reset, cmd_addr };
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`ifdef USE_TRAP
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`ifdef USE_TRAP
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//
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//
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| Line 452... |
Line 454... |
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//
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//
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// The programmable interrupt controller peripheral
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// The programmable interrupt controller peripheral
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//
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//
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wire pic_interrupt;
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wire pic_interrupt;
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wire [6:0] int_vector;
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wire [(5+EXTERNAL_INTERRUPTS):0] int_vector;
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assign int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
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assign int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
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jif_int, cache_int };
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jif_int, cache_int };
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icontrol #(7) pic(i_clk, cpu_reset,
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icontrol #(6+EXTERNAL_INTERRUPTS) pic(i_clk, cpu_reset,
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(sys_cyc)&&(sys_stb)&&(sys_we)
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(sys_cyc)&&(sys_stb)&&(sys_we)
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&&(sys_addr==`INTCTRL),
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&&(sys_addr==`INTCTRL),
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sys_data, pic_data,
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sys_data, pic_data,
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int_vector, pic_interrupt);
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int_vector, pic_interrupt);
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reg pic_ack;
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reg pic_ack;
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