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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Diff between revs 25 and 34

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Rev 25 Rev 34
Line 132... Line 132...
                // Our one outgoing interrupt
                // Our one outgoing interrupt
                o_ext_int,
                o_ext_int,
                // Wishbone slave interface for debugging purposes
                // Wishbone slave interface for debugging purposes
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
        parameter       RESET_ADDRESS=32'h0100000;
        parameter       RESET_ADDRESS=32'h0100000, START_HALTED=1,
 
                        EXTERNAL_INTERRUPTS=1;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [31:0]   o_wb_addr;
        output  wire    [31:0]   o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        // Incoming interrupts
        // Incoming interrupts
        input                   i_ext_int;
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
        // Outgoing interrupt
        // Outgoing interrupt
        output  wire            o_ext_int;
        output  wire            o_ext_int;
        // Wishbone slave
        // Wishbone slave
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
        input           [31:0]   i_dbg_data;
        input           [31:0]   i_dbg_data;
Line 209... Line 210...
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
        //
        //
        initial cmd_halt  = 1'b1;
        initial cmd_halt  = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        cmd_halt <= 1'b1;
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
                else if (dbg_cmd_write)
                else if (dbg_cmd_write)
                        cmd_halt <= dbg_idata[10];
                        cmd_halt <= dbg_idata[10];
                else if ((cmd_step)||(cpu_break))
                else if ((cmd_step)||(cpu_break))
                        cmd_halt  <= 1'b1;
                        cmd_halt  <= 1'b1;
 
 
Line 232... Line 233...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (dbg_cmd_write)
                if (dbg_cmd_write)
                        cmd_addr <= dbg_idata[5:0];
                        cmd_addr <= dbg_idata[5:0];
 
 
        wire    cpu_reset;
        wire    cpu_reset;
        assign  cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
        assign  cpu_reset = (cmd_reset)||(wdt_reset);
 
 
        wire    cpu_halt, cpu_dbg_stall;
        wire    cpu_halt, cpu_dbg_stall;
        assign  cpu_halt = (cmd_halt)&&(~cmd_step);
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
        wire    [31:0]   pic_data;
        wire    [31:0]   pic_data;
        wire    [31:0]   cmd_data;
        wire    [31:0]   cmd_data;
        // Values:
        // Values:
        //      0x0003f -> cmd_addr mask
        //      0x0003f -> cmd_addr mask
        //      0x00040 -> reset
        //      0x00040 -> reset
        //      0x00080 -> interrrupts enabled
        //      0x00080 -> PIC interrrupts enabled
        //      0x00100 -> cmd_step
        //      0x00100 -> cmd_step
        //      0x00200 -> cmd_stall
        //      0x00200 -> cmd_stall
        //      0x00400 -> cmd_halt
        //      0x00400 -> cmd_halt
        //      0x00800 -> cmd_clear_pf_cache
        //      0x00800 -> cmd_clear_pf_cache
        //      0x01000 -> cc.sleep
        //      0x01000 -> cc.sleep
        //      0x02000 -> cc.gie
        //      0x02000 -> cc.gie
        //      0x10000 -> External interrupt line is high
        //      0x10000 -> External interrupt line is high
        assign  cmd_data = { 15'h00, i_ext_int, 2'b00, cpu_dbg_cc,
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
 
                        2'b00, cpu_dbg_cc,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        pic_data[15], cpu_reset, cmd_addr };
                        pic_data[15], cpu_reset, cmd_addr };
 
 
`ifdef  USE_TRAP
`ifdef  USE_TRAP
        //
        //
Line 452... Line 454...
 
 
        //
        //
        // The programmable interrupt controller peripheral
        // The programmable interrupt controller peripheral
        //
        //
        wire            pic_interrupt;
        wire            pic_interrupt;
        wire    [6:0]    int_vector;
        wire    [(5+EXTERNAL_INTERRUPTS):0]      int_vector;
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
                                        jif_int, cache_int };
                                        jif_int, cache_int };
        icontrol #(7)   pic(i_clk, cpu_reset,
        icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
                                (sys_cyc)&&(sys_stb)&&(sys_we)
                                (sys_cyc)&&(sys_stb)&&(sys_we)
                                        &&(sys_addr==`INTCTRL),
                                        &&(sys_addr==`INTCTRL),
                                sys_data, pic_data,
                                sys_data, pic_data,
                                int_vector, pic_interrupt);
                                int_vector, pic_interrupt);
        reg     pic_ack;
        reg     pic_ack;

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