OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Diff between revs 36 and 38

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 36 Rev 38
Line 285... Line 285...
        //      0x10000 -> External interrupt line is high
        //      0x10000 -> External interrupt line is high
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
                        2'b00, cpu_dbg_cc,
                        2'b00, cpu_dbg_cc,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
                        pic_data[15], cpu_reset, cmd_addr };
                        pic_data[15], cpu_reset, cmd_addr };
 
        wire    cpu_gie;
 
        assign  cpu_gie = cpu_dbg_cc[1];
 
 
`ifdef  USE_TRAP
`ifdef  USE_TRAP
        //
        //
        // The TRAP peripheral
        // The TRAP peripheral
        //
        //
Line 366... Line 368...
        // be reset any time a task is given control of the CPU.
        // be reset any time a task is given control of the CPU.
        //
        //
        // User task counter
        // User task counter
        wire            utc_ack, utc_stall, utc_int;
        wire            utc_ack, utc_stall, utc_int;
        wire    [31:0]   utc_data;
        wire    [31:0]   utc_data;
        zipcounter      utask_ctr(i_clk,(~cpu_halt), sys_cyc,
        zipcounter      utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                utc_ack, utc_stall, utc_data, utc_int);
                                utc_ack, utc_stall, utc_data, utc_int);
 
 
        // User Op-Stall counter
        // User Op-Stall counter
        wire            uoc_ack, uoc_stall, uoc_int;
        wire            uoc_ack, uoc_stall, uoc_int;
        wire    [31:0]   uoc_data;
        wire    [31:0]   uoc_data;
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
 
 
        // User PreFetch-Stall counter
        // User PreFetch-Stall counter
        wire            upc_ack, upc_stall, upc_int;
        wire            upc_ack, upc_stall, upc_int;
        wire    [31:0]   upc_data;
        wire    [31:0]   upc_data;
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                upc_ack, upc_stall, upc_data, upc_int);
                                upc_ack, upc_stall, upc_data, upc_int);
 
 
        // User instruction counter
        // User instruction counter
        wire            uic_ack, uic_stall, uic_int;
        wire            uic_ack, uic_stall, uic_int;
        wire    [31:0]   uic_data;
        wire    [31:0]   uic_data;
        zipcounter      uins_ctr(i_clk,(cpu_i_count), sys_cyc,
        zipcounter      uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc,
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
                                        sys_we, sys_data,
                                        sys_we, sys_data,
                                uic_ack, uic_stall, uic_data, uic_int);
                                uic_ack, uic_stall, uic_data, uic_int);
 
 
        // A little bit of pre-cleanup (actr = accounting counters)
        // A little bit of pre-cleanup (actr = accounting counters)

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.