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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Diff between revs 38 and 48

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Rev 38 Rev 48
Line 160... Line 160...
                // Our one outgoing interrupt
                // Our one outgoing interrupt
                o_ext_int,
                o_ext_int,
                // Wishbone slave interface for debugging purposes
                // Wishbone slave interface for debugging purposes
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
        parameter       RESET_ADDRESS=32'h0100000, START_HALTED=1,
        parameter       RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
                        EXTERNAL_INTERRUPTS=1;
                        LGICACHE=6, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
 
                        // Derived parameters
 
                        AW=ADDRESS_WIDTH;
        input   i_clk, i_rst;
        input   i_clk, i_rst;
        // Wishbone master
        // Wishbone master
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
        output  wire    [31:0]   o_wb_addr;
        output  wire    [(AW-1):0]       o_wb_addr;
        output  wire    [31:0]   o_wb_data;
        output  wire    [31:0]   o_wb_data;
        input                   i_wb_ack, i_wb_stall;
        input                   i_wb_ack, i_wb_stall;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        input                   i_wb_err;
        input                   i_wb_err;
        // Incoming interrupts
        // Incoming interrupts
Line 211... Line 213...
        // 
        // 
        //
        //
        //
        //
        wire    sys_cyc, sys_stb, sys_we;
        wire    sys_cyc, sys_stb, sys_we;
        wire    [4:0]    sys_addr;
        wire    [4:0]    sys_addr;
        wire    [31:0]   cpu_addr;
        wire    [(AW-1):0]       cpu_addr;
        wire    [31:0]   sys_data;
        wire    [31:0]   sys_data;
        wire            sys_ack, sys_stall;
        wire            sys_ack, sys_stall;
 
 
        //
        //
        // The external debug interface
        // The external debug interface
Line 441... Line 443...
        //
        //
        wire            dmac_int, dmac_stb, dc_err;
        wire            dmac_int, dmac_stb, dc_err;
        wire    [31:0]   dmac_data;
        wire    [31:0]   dmac_data;
        wire            dmac_ack, dmac_stall;
        wire            dmac_ack, dmac_stall;
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
        wire    [31:0]   dc_data, dc_addr;
        wire    [31:0]   dc_data;
 
        wire    [(AW-1):0]       dc_addr;
        wire            cpu_gbl_cyc;
        wire            cpu_gbl_cyc;
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
        wbdmac  dma_controller(i_clk,
        wbdmac  #(AW) dma_controller(i_clk,
                                sys_cyc, dmac_stb, sys_we,
                                sys_cyc, dmac_stb, sys_we,
                                        sys_addr[1:0], sys_data,
                                        sys_addr[1:0], sys_data,
                                        dmac_ack, dmac_stall, dmac_data,
                                        dmac_ack, dmac_stall, dmac_data,
                                // Need the outgoing DMAC wishbone bus
                                // Need the outgoing DMAC wishbone bus
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
Line 556... Line 559...
        wire    [31:0]   cpu_data, wb_data;
        wire    [31:0]   cpu_data, wb_data;
        wire            cpu_ack, cpu_stall, cpu_err;
        wire            cpu_ack, cpu_stall, cpu_err;
        wire    [31:0]   cpu_dbg_data;
        wire    [31:0]   cpu_dbg_data;
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
                                        &&(dbg_we)&&(dbg_addr));
                                        &&(dbg_we)&&(dbg_addr));
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
 
                thecpu(i_clk, cpu_reset, pic_interrupt,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
                                cpu_dbg_cc, cpu_break,
                                cpu_dbg_cc, cpu_break,
                        cpu_gbl_cyc, cpu_gbl_stb,
                        cpu_gbl_cyc, cpu_gbl_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
                                cpu_lcl_cyc, cpu_lcl_stb,
Line 610... Line 614...
        // cache gets access to the bus--the CPU will be stuck until the 
        // cache gets access to the bus--the CPU will be stuck until the 
        // flash cache is finished with the bus.
        // flash cache is finished with the bus.
        wire            ext_cyc, ext_stb, ext_we, ext_err;
        wire            ext_cyc, ext_stb, ext_we, ext_err;
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
                                cpu_ext_err;
                                cpu_ext_err;
        wire    [31:0]   ext_addr, ext_odata;
        wire    [(AW-1):0]       ext_addr;
        wbpriarbiter #(32,32) dmacvcpu(i_clk, i_rst,
        wire    [31:0]           ext_odata;
 
        wbpriarbiter #(32,AW) dmacvcpu(i_clk, i_rst,
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
                                        dc_ack, dc_stall, dc_err,
                                        dc_ack, dc_stall, dc_err,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                                ext_ack, ext_stall, ext_err);
                                ext_ack, ext_stall, ext_err);
 
 
`ifdef  DELAY_EXT_BUS
`ifdef  DELAY_EXT_BUS
        busdelay #(32,32) extbus(i_clk,
        busdelay #(AW,32) extbus(i_clk,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
                                ext_ack, ext_stall, ext_idata, ext_err,
                                ext_ack, ext_stall, ext_idata, ext_err,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                                i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
                                i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
`else
`else

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