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Line 80... |
// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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`include "cpudefs.v"
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//
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// While I hate adding delays to any bus access, this next delay is required
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// While I hate adding delays to any bus access, this next delay is required
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// to make timing close in my Basys-3 design.
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// to make timing close in my Basys-3 design.
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`define DELAY_DBG_BUS
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`define DELAY_DBG_BUS
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// On my previous version, I needed to add a delay to access the external
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// On my previous version, I needed to add a delay to access the external
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// bus. Activate the define below and that delay will be put back into place.
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// bus. Activate the define below and that delay will be put back into place.
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// ADDRESS:
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// ADDRESS:
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// 5 PERIPHERAL-BIT
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// 5 PERIPHERAL-BIT
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// [4:0] REGISTER-ADDR
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// [4:0] REGISTER-ADDR
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// DBGDATA
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// DBGDATA
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// read/writes internal registers
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// read/writes internal registers
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//
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//
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//
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module zipsystem(i_clk, i_rst,
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module zipsystem(i_clk, i_rst,
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// Wishbone master interface from the CPU
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// Wishbone master interface from the CPU
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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// Incoming interrupts
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// Incoming interrupts
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i_ext_int,
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i_ext_int,
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// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data
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o_cpu_debug);
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`ifdef DEBUG_SCOPE
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, o_cpu_debug
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`endif
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);
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parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
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parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
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LGICACHE=6, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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LGICACHE=12, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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// Derived parameters
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// Derived parameters
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AW=ADDRESS_WIDTH;
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AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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Line 192... |
input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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output wire o_dbg_ack;
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output wire o_dbg_ack;
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output wire o_dbg_stall;
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output wire o_dbg_stall;
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output wire [31:0] o_dbg_data;
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output wire [31:0] o_dbg_data;
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//
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//
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`ifdef DEBUG_SCOPE
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output wire [31:0] o_cpu_debug;
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output wire [31:0] o_cpu_debug;
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`endif
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wire [31:0] ext_idata;
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wire [31:0] ext_idata;
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// Delay the debug port by one clock, to meet timing requirements
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// Delay the debug port by one clock, to meet timing requirements
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wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
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Line 475... |
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
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wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
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wire [31:0] dc_data;
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wire [31:0] dc_data;
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wire [(AW-1):0] dc_addr;
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wire [(AW-1):0] dc_addr;
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wire cpu_gbl_cyc;
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wire cpu_gbl_cyc;
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assign dmac_stb = (sys_stb)&&(sys_addr[4]);
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assign dmac_stb = (sys_stb)&&(sys_addr[4]);
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// `define INCLUDE_DMA_CONTROLLER
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`define INCLUDE_DMA_CONTROLLER
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`ifdef INCLUDE_DMA_CONTROLLER
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`ifdef INCLUDE_DMA_CONTROLLER
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wbdmac #(AW) dma_controller(i_clk,
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wbdmac #(AW) dma_controller(i_clk,
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sys_cyc, dmac_stb, sys_we,
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sys_cyc, dmac_stb, sys_we,
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sys_addr[1:0], sys_data,
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sys_addr[1:0], sys_data,
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dmac_ack, dmac_stall, dmac_data,
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dmac_ack, dmac_stall, dmac_data,
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Line 615... |
cpu_gbl_cyc, cpu_gbl_stb,
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cpu_gbl_cyc, cpu_gbl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_we, cpu_addr, cpu_data,
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cpu_we, cpu_addr, cpu_data,
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cpu_ack, cpu_stall, wb_data,
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cpu_ack, cpu_stall, wb_data,
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cpu_err,
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cpu_err,
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cpu_op_stall, cpu_pf_stall, cpu_i_count,
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cpu_op_stall, cpu_pf_stall, cpu_i_count
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o_cpu_debug);
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`ifdef DEBUG_SCOPE
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, o_cpu_debug
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`endif
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);
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// Now, arbitrate the bus ... first for the local peripherals
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// Now, arbitrate the bus ... first for the local peripherals
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// For the debugger to have access to the local system bus, the
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// For the debugger to have access to the local system bus, the
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// following must be true:
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// following must be true:
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// (dbg_cyc) The debugger must request the bus
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// (dbg_cyc) The debugger must request the bus
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