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[/] [zipcpu/] [trunk/] [sim/] [verilator/] [div_tb.cpp] - Diff between revs 207 and 209

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Line 1... Line 1...
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    div_tb.cpp
// Filename:    div_tb.cpp
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
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//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
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// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
#include <signal.h>
#include <signal.h>
#include <stdint.h>
#include <stdint.h>
#include <time.h>
#include <time.h>
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#include <ctype.h>
#include <ctype.h>
 
 
#include "verilated.h"
#include "verilated.h"
#include "Vdiv.h"
#include "Vdiv.h"
 
 
 
#ifdef  NEW_VERILATOR
 
#define VVAR(A) div__DOT_ ## A
 
#else
 
#define VVAR(A) v__DOT_ ## A
 
#endif
 
 
 
#define r_busy          VVAR(_r_busy)
 
#define pre_sign        VVAR(_pre_sign)
 
#define r_sign          VVAR(_r_sign)
 
#define r_z             VVAR(_r_z)
 
#define r_bit           VVAR(_r_bit)
 
#define last_bit        VVAR(_last_bit)
 
#define r_dividend      VVAR(_r_dividend)
 
#define r_divisor       VVAR(_r_divisor)
 
#define vdiff           VVAR(_diff)
 
 
#include "testb.h"
#include "testb.h"
// #include "twoc.h"
// #include "twoc.h"
 
 
#define DIVASSERT(A) do { if (!(A)) { closetrace(); } assert(A); } while(0)
#define DIVASSERT(A) do { if (!(A)) { closetrace(); } assert(A); } while(0)
 
 
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                } *str = '\0';
                } *str = '\0';
        }
        }
 
 
        void    dbgdump(void) {
        void    dbgdump(void) {
                char    outstr[2048], *s;
                char    outstr[2048], *s;
                sprintf(outstr, "Tick %4ld %s%s%s%s%s%s%s %2d(%s= 0)",
                sprintf(outstr, "Tick %4lld %s%s%s%s%s%s%s %2d(%s= 0)",
                        m_tickcount,
                        (unsigned long long)m_tickcount,
                        (m_core->o_busy)?"B":" ",
                        (m_core->o_busy)?"B":" ",
                        (m_core->v__DOT__r_busy)?"R":" ",
                        (m_core->r_busy)?"R":" ",
                        (m_core->o_valid)?"V":" ",
                        (m_core->o_valid)?"V":" ",
                        (m_core->i_wr)?"W":" ",
                        (m_core->i_wr)?"W":" ",
                        (m_core->v__DOT__pre_sign)?"+":" ",
                        (m_core->pre_sign)?"+":" ",
                        (m_core->v__DOT__r_sign)?"-":" ",
                        (m_core->r_sign)?"-":" ",
                        (m_core->v__DOT__r_z)?"Z":" ",
                        (m_core->r_z)?"Z":" ",
                        m_core->v__DOT__r_bit,
                        m_core->r_bit,
                        (m_core->v__DOT__last_bit)?"=":"!");
                        (m_core->last_bit)?"=":"!");
                s = &outstr[strlen(outstr)];
                s = &outstr[strlen(outstr)];
                sprintf(s, "%s\n%10s %40s",s, "Div","");
                sprintf(s, "%s\n%10s %40s",s, "Div","");
                        s = &s[strlen(s)];
                        s = &s[strlen(s)];
                bprint( s, 32, m_core->v__DOT__r_dividend);
                bprint( s, 32, m_core->r_dividend);
                        s=&s[strlen(s)];
                        s=&s[strlen(s)];
                sprintf(s, "%s\n%10s ",s, "Div"); s = &s[strlen(s)];
                sprintf(s, "%s\n%10s ",s, "Div"); s = &s[strlen(s)];
                bprint( s, 64, m_core->v__DOT__r_divisor);
                bprint( s, 64, m_core->r_divisor);
                        s=&s[strlen(s)];
                        s=&s[strlen(s)];
                sprintf(s, "%s\n%10s %40s",s, "Q",""); s=&s[strlen(s)];
                sprintf(s, "%s\n%10s %40s",s, "Q",""); s=&s[strlen(s)];
                bprint( s, 32, m_core->o_quotient); s = &s[strlen(s)];
                bprint( s, 32, m_core->o_quotient); s = &s[strlen(s)];
                sprintf(s, "%s\n%10s %38s",s, "Diff","");
                sprintf(s, "%s\n%10s %38s",s, "Diff","");
                        s=&s[strlen(s)];
                        s=&s[strlen(s)];
                bprint( s, 33, m_core->v__DOT__diff); s = &s[strlen(s)];
                bprint( s, 33, m_core->vdiff); s = &s[strlen(s)];
                strcat(s, "\n");
                strcat(s, "\n");
                puts(outstr);
                puts(outstr);
        }
        }
 
 
        void    tick(void) {
        void    tick(void) {
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                // The test bench is supposed to assert that we are idle when
                // The test bench is supposed to assert that we are idle when
                // we come in here.
                // we come in here.
                DIVASSERT(m_core->o_busy == 0);
                DIVASSERT(m_core->o_busy == 0);
 
 
                // Request a divide
                // Request a divide
                m_core->i_rst = 0;
                m_core->i_reset = 0;
                m_core->i_wr = 1;
                m_core->i_wr = 1;
                m_core->i_signed = (issigned)?1:0;
                m_core->i_signed = (issigned)?1:0;
                m_core->i_numerator = n;
                m_core->i_numerator = n;
                m_core->i_denominator = d;
                m_core->i_denominator = d;
 
 

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