OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Diff between revs 117 and 122

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 117 Rev 122
Line 136... Line 136...
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+
+
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
@@ -21,7 +21,7 @@
@@ -21,7 +21,7 @@
 #ifndef GCC_AARCH64_LINUX_H
 #ifndef GCC_AARCH64_LINUX_H
 #define GCC_AARCH64_LINUX_H
 #define GCC_AARCH64_LINUX_H
 
 
Line 148... Line 148...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
 
 
 #undef  ASAN_CC1_SPEC
 #undef  ASAN_CC1_SPEC
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
@@ -23,8 +23,8 @@
@@ -23,8 +23,8 @@
 #define EXTRA_SPECS \
 #define EXTRA_SPECS \
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
 
 
Line 162... Line 162...
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif DEFAULT_LIBC == LIBC_GLIBC
 #elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
@@ -68,8 +68,8 @@
@@ -68,8 +68,8 @@
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
 
 
 #undef  GLIBC_DYNAMIC_LINKER
 #undef  GLIBC_DYNAMIC_LINKER
Line 176... Line 176...
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
 
 
 #define GLIBC_DYNAMIC_LINKER \
 #define GLIBC_DYNAMIC_LINKER \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
@@ -62,7 +62,7 @@
@@ -62,7 +62,7 @@
 
 
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
 
 
Line 188... Line 188...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
    %{static:-Bstatic} \
    %{static:-Bstatic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -45,7 +45,7 @@
@@ -45,7 +45,7 @@
   %{shared:-G -Bdynamic} \
   %{shared:-G -Bdynamic} \
   %{!shared: %{!static: \
   %{!shared: %{!static: \
    %{rdynamic:-export-dynamic} \
    %{rdynamic:-export-dynamic} \
Line 200... Line 200...
+   -dynamic-linker /lib/ld-uClibc.so.0} \
+   -dynamic-linker /lib/ld-uClibc.so.0} \
    %{static}} -init __init -fini __fini"
    %{static}} -init __init -fini __fini"
 
 
 #undef TARGET_SUPPORTS_SYNC_CALLS
 #undef TARGET_SUPPORTS_SYNC_CALLS
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -102,7 +102,7 @@
@@ -102,7 +102,7 @@
 #undef CRIS_DEFAULT_CPU_VERSION
 #undef CRIS_DEFAULT_CPU_VERSION
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 
 
Line 212... Line 212...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef CRIS_LINK_SUBTARGET_SPEC
 #undef CRIS_LINK_SUBTARGET_SPEC
 #define CRIS_LINK_SUBTARGET_SPEC \
 #define CRIS_LINK_SUBTARGET_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
@@ -129,9 +129,9 @@
@@ -129,9 +129,9 @@
 #endif
 #endif
 
 
 #if FBSD_MAJOR < 6
 #if FBSD_MAJOR < 6
Line 227... Line 227...
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
 #endif
 #endif
 
 
 /* NOTE: The freebsd-spec.h header is included also for various
 /* NOTE: The freebsd-spec.h header is included also for various
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
@@ -34,7 +34,7 @@
@@ -34,7 +34,7 @@
 #define ENDFILE_SPEC \
 #define ENDFILE_SPEC \
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
 
 
Line 239... Line 239...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -22,7 +22,7 @@
@@ -22,7 +22,7 @@
 #define GNU_USER_LINK_EMULATION "elf_i386"
 #define GNU_USER_LINK_EMULATION "elf_i386"
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
Line 251... Line 251...
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
 
 
 #undef STARTFILE_SPEC
 #undef STARTFILE_SPEC
 #if defined HAVE_LD_PIE
 #if defined HAVE_LD_PIE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
@@ -22,6 +22,6 @@
@@ -22,6 +22,6 @@
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
 
 
Line 264... Line 264...
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
@@ -19,4 +19,4 @@
@@ -19,4 +19,4 @@
 <http://www.gnu.org/licenses/>.  */
 <http://www.gnu.org/licenses/>.  */
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
@@ -27,6 +27,6 @@
@@ -27,6 +27,6 @@
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
 
 
Line 286... Line 286...
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -20,4 +20,4 @@
@@ -20,4 +20,4 @@
 <http://www.gnu.org/licenses/>.  */
 <http://www.gnu.org/licenses/>.  */
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386"
 #define GNU_USER_LINK_EMULATION "elf_i386"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -55,7 +55,7 @@
@@ -55,7 +55,7 @@
 /* Define this for shared library support because it isn't in the main
 /* Define this for shared library support because it isn't in the main
    linux.h file.  */
    linux.h file.  */
 
 
Line 307... Line 307...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
@@ -32,4 +32,4 @@
@@ -32,4 +32,4 @@
 
 
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -31,5 +31,4 @@
@@ -31,5 +31,4 @@
   while (0)
   while (0)
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-
-
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
--- gcc-5.3.0-original/gcc/config/linux.h       2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/linux.h       2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
@@ -73,10 +73,10 @@
@@ -73,10 +73,10 @@
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
    supporting both 32-bit and 64-bit compilation.  */
    supporting both 32-bit and 64-bit compilation.  */
Line 344... Line 344...
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
@@ -67,7 +67,7 @@
@@ -67,7 +67,7 @@
    %{shared:-shared} \
    %{shared:-shared} \
    %{symbolic:-Bsymbolic} \
    %{symbolic:-Bsymbolic} \
    %{rdynamic:-export-dynamic} \
    %{rdynamic:-export-dynamic} \
Line 356... Line 356...
+   -dynamic-linker /lib/ld-linux.so.2"
+   -dynamic-linker /lib/ld-linux.so.2"
 
 
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -71,7 +71,7 @@
@@ -71,7 +71,7 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 368... Line 368...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "-m m68kelf %{shared} \
 #define LINK_SPEC "-m m68kelf %{shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-04-06 17:56:01.475918570 -0400
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
@@ -28,7 +28,7 @@
@@ -28,7 +28,7 @@
 #undef TLS_NEEDS_GOT
 #undef TLS_NEEDS_GOT
 #define TLS_NEEDS_GOT 1
 #define TLS_NEEDS_GOT 1
 
 
Line 380... Line 380...
+#define DYNAMIC_LINKER "/lib/ld.so.1"
+#define DYNAMIC_LINKER "/lib/ld.so.1"
 #undef  SUBTARGET_EXTRA_SPECS
 #undef  SUBTARGET_EXTRA_SPECS
 #define SUBTARGET_EXTRA_SPECS \
 #define SUBTARGET_EXTRA_SPECS \
   { "dynamic_linker", DYNAMIC_LINKER }
   { "dynamic_linker", DYNAMIC_LINKER }
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -22,20 +22,20 @@
@@ -22,20 +22,20 @@
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
 
 
 #define GLIBC_DYNAMIC_LINKER32 \
 #define GLIBC_DYNAMIC_LINKER32 \
Line 410... Line 410...
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
 
 
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
 #define GNU_USER_DYNAMIC_LINKERN32 \
 #define GNU_USER_DYNAMIC_LINKERN32 \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-04-02 11:53:47.213604913 -0400
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
@@ -32,7 +32,7 @@
@@ -32,7 +32,7 @@
 #undef  ASM_SPEC
 #undef  ASM_SPEC
 #define ASM_SPEC ""
 #define ASM_SPEC ""
 
 
Line 422... Line 422...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
@@ -37,7 +37,7 @@
@@ -37,7 +37,7 @@
 /* Define this for shared library support because it isn't in the main
 /* Define this for shared library support because it isn't in the main
    linux.h file.  */
    linux.h file.  */
 
 
Line 434... Line 434...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
@@ -357,14 +357,14 @@
@@ -357,14 +357,14 @@
 #undef LINK_OS_DEFAULT_SPEC
 #undef LINK_OS_DEFAULT_SPEC
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 
 
Line 457... Line 457...
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif DEFAULT_LIBC == LIBC_GLIBC
 #elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
@@ -757,8 +757,8 @@
@@ -757,8 +757,8 @@
 
 
 #define LINK_START_LINUX_SPEC ""
 #define LINK_START_LINUX_SPEC ""
 
 
Line 471... Line 471...
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
@@ -60,8 +60,8 @@
@@ -60,8 +60,8 @@
 #define MULTILIB_DEFAULTS { "m31" }
 #define MULTILIB_DEFAULTS { "m31" }
 #endif
 #endif
 
 
Line 485... Line 485...
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC \
 #define LINK_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -43,7 +43,7 @@
@@ -43,7 +43,7 @@
 
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
 
Line 497... Line 497...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #undef SUBTARGET_LINK_EMUL_SUFFIX
 #undef SUBTARGET_LINK_EMUL_SUFFIX
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
@@ -84,8 +84,8 @@
@@ -84,8 +84,8 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 520... Line 520...
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
   %{!shared: \
   %{!shared: \
     %{!static: \
     %{!static: \
       %{rdynamic:-export-dynamic} \
       %{rdynamic:-export-dynamic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
@@ -83,7 +83,7 @@
@@ -83,7 +83,7 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 532... Line 532...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
@@ -41,7 +41,7 @@
@@ -41,7 +41,7 @@
   %{!shared: \
   %{!shared: \
     %{!static: \
     %{!static: \
       %{rdynamic:-export-dynamic} \
       %{rdynamic:-export-dynamic} \
Line 544... Line 544...
+      -dynamic-linker /lib/ld.so.1} \
+      -dynamic-linker /lib/ld.so.1} \
     %{static:-static}}"
     %{static:-static}}"
 
 
 #undef  WCHAR_TYPE
 #undef  WCHAR_TYPE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-04-02 11:53:47.217604879 -0400
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-04-06 17:56:01.479918541 -0400
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
@@ -44,7 +44,7 @@
@@ -44,7 +44,7 @@
   %{mlongcalls:--longcalls} \
   %{mlongcalls:--longcalls} \
   %{mno-longcalls:--no-longcalls}"
   %{mno-longcalls:--no-longcalls}"
 
 
Line 694... Line 694...
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-04-01 06:26:30.217272207 -0400
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-04-06 17:47:47.255349663 -0400
@@ -0,0 +1,2341 @@
@@ -0,0 +1,2099 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   zip.c
+// Filename:   zip.c
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 771... Line 771...
+#include "calls.h"
+#include "calls.h"
+#include "langhooks.h"
+#include "langhooks.h"
+#include "optabs.h"
+#include "optabs.h"
+#include "explow.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "emit-rtl.h"
 
+#include "ifcvt.h"
+
+
+// #include "tmp_p.h"
+// #include "tmp_p.h"
+#include "target.h"
+#include "target.h"
+#include "target-def.h"
+#include "target-def.h"
+// #include "tm-constrs.h"
+// #include "tm-constrs.h"
+// #include "tm-preds.h"
+#include "tm-preds.h"
+
+
+#include "diagnostic.h"
+#include "diagnostic.h"
+// #include "integrate.h"
+// #include "integrate.h"
+
+
+// static int  zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
+// static int  zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
+// static      bool    zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
+// static      bool    zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
+static bool    zip_return_in_memory(const_tree, const_tree);
+static bool    zip_return_in_memory(const_tree, const_tree);
+static bool    zip_frame_pointer_required(void);
+static bool    zip_frame_pointer_required(void);
+// static      bool    zip_must_pass_in_stack(enum machine_mode, const_tree);
 
+
+
+// static      void    zip_setup_incoming_varargs(CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
 
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
+               const_tree type, bool named);
+               const_tree type, bool named);
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named);
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named);
+
+
+static void    zip_asm_trampoline_template(FILE *);
+static void    zip_asm_trampoline_template(FILE *);
+static void    zip_trampoline_init(rtx, tree, rtx);
+static void    zip_trampoline_init(rtx, tree, rtx);
+static void    zip_init_builtins(void);
+static void    zip_init_builtins(void);
+static tree zip_builtin_decl(unsigned, bool);
+static tree zip_builtin_decl(unsigned, bool);
+// static void zip_asm_output_anchor(rtx x);
+// static void zip_asm_output_anchor(rtx x);
+       void    zip_asm_output_def(FILE *s, const char *n, const char *v);
+       void    zip_asm_output_def(FILE *s, const char *n, const char *v);
+       void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
 
+static rtx     zip_expand_builtin(tree exp, rtx target, rtx subtarget,
+static rtx     zip_expand_builtin(tree exp, rtx target, rtx subtarget,
+                       enum machine_mode tmode, int    ignore);
+                       enum machine_mode tmode, int    ignore);
+static bool    zip_scalar_mode_supported_p(enum machine_mode mode);
+static bool    zip_scalar_mode_supported_p(enum machine_mode mode);
+static bool    zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
+static bool    zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
+static int     zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
+static int     zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
+static bool    zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
+static bool    zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
+static unsigned HOST_WIDE_INT  zip_const_anchor = 0x20000;
+static unsigned HOST_WIDE_INT  zip_const_anchor = 0x20000;
+static          HOST_WIDE_INT  zip_min_opb_imm = -0x200000;
+static          HOST_WIDE_INT  zip_min_opb_imm = -0x20000;
+static          HOST_WIDE_INT  zip_max_opb_imm =  0x1fffff;
+static          HOST_WIDE_INT  zip_max_opb_imm =  0x1ffff;
+static          HOST_WIDE_INT  zip_min_anchor_offset = -0x20000;
+static          HOST_WIDE_INT  zip_min_anchor_offset = -0x20000;
+static          HOST_WIDE_INT  zip_max_anchor_offset =  0x1ffff;
+static          HOST_WIDE_INT  zip_max_anchor_offset =  0x1ffff;
+static          HOST_WIDE_INT  zip_min_mov_offset = -0x1000;
+static          HOST_WIDE_INT  zip_min_mov_offset = -0x1000;
+static          HOST_WIDE_INT  zip_max_mov_offset =  0x0fff;
+static          HOST_WIDE_INT  zip_max_mov_offset =  0x0fff;
+static int     zip_sched_issue_rate(void) { return 1; }
+static int     zip_sched_issue_rate(void) { return 1; }
Line 822... Line 820...
+static void    zip_override_options(void);
+static void    zip_override_options(void);
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
+static bool    zip_cannot_modify_jumps_p(void);
+static bool    zip_cannot_modify_jumps_p(void);
 
+#ifdef HAVE_cc0
 
+       void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
 
+#error "We're not supposed to have CC0 anymore"
 
+#else
 
+static bool    zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
 
+#endif
+
+
+
+
+#define        ALL_DEBUG_OFF   false
+#define        ALL_DEBUG_OFF   false
+#define        ALL_DEBUG_ON    false
+#define        ALL_DEBUG_ON    false
+
+
Line 1086... Line 1090...
+       // Use a GCC global to determine our answer
+       // Use a GCC global to determine our answer
+       if (cfun->calls_alloca)
+       if (cfun->calls_alloca)
+               return true;
+               return true;
+       return (frame_pointer_needed);
+       return (frame_pointer_needed);
+/*
+/*
+       fprintf(stderr, "ZIP_FRAME_POINTER_REQUIRED()\n");
 
+       if (frame_pointer_needed) {
 
+               fprintf(stderr, "FRAME_POINTER_NEEDED is true\n");
 
+               zip_debug_rtx(frame_pointer_rtx);
 
+               if (frame_pointer_rtx == NULL_RTX)
 
+                       return true;
 
+               if (GET_CODE(frame_pointer_rtx)==PLUS) {
 
+                       if ((REG_P(XEXP(frame_pointer_rtx,0)))
 
+                               &&(REGNO(XEXP(frame_pointer_rtx, 0))==zip_SP)
 
+                               &&(CONST_INT_P(XEXP(frame_pointer_rtx,1))))
 
+                               return false;
 
+                       if ((REG_P(XEXP(frame_pointer_rtx,1)))
 
+                               &&(REGNO(XEXP(frame_pointer_rtx, 1))==zip_SP)
 
+                               &&(CONST_INT_P(XEXP(frame_pointer_rtx,0))))
 
+                               return false;
 
+                       return true;
 
+               } else if ((REG_P(frame_pointer_rtx))
 
+                               &&(REGNO(frame_pointer_rtx) == zip_SP))
 
+                       return false;
 
+               return true;
 
+       } else return false;
 
+*/
+*/
+}
+}
+
+
+/* Determine whether or not a register needs to be saved on the stack or not.
+/* Determine whether or not a register needs to be saved on the stack or not.
+ */
+ */
Line 1187... Line 1170...
+       cfun->machine->sp_fp_offset = args_size + cfun->machine->local_vars_size;
+       cfun->machine->sp_fp_offset = args_size + cfun->machine->local_vars_size;
+       cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
+       cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
+                       + cfun->machine->saved_reg_size
+                       + cfun->machine->saved_reg_size
+                       + args_size;
+                       + args_size;
+
+
+       /*
 
+       if (cfun->machine->fp_needed)
 
+               frame_pointer_rtx = gen_rtx_REG(Pmode, zip_FP);
 
+       else
 
+               frame_pointer_rtx = plus_constant(Pmode, gen_rtx_REG(Pmode, zip_SP),
 
+                       cfun->machine->sp_fp_offset);
 
+       */
 
+}
+}
+
+
+void
+void
+zip_expand_prologue(void) {
+zip_expand_prologue(void) {
+       rtx     insn;
+       rtx     insn;
Line 1380... Line 1356...
+       }
+       }
+
+
+       return ret;
+       return ret;
+}
+}
+
+
+/* Return non-zero if the function argument described by TYPE is to be passed
 
+ * by reference.
 
+ */
 
+/*
 
+static bool
 
+zip_pass_by_reference(CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
 
+               enum machine_mode mode, const_tree type,
 
+               bool name ATTRIBUTE_UNUSED) {
 
+       unsigned        HOST_WIDE_INT   size;
 
+
 
+       if (type) {
 
+               if (AGGREGATE_TYPE_P(type)) {
 
+                       return TRUE;
 
+               } size = int_size_in_bytes(type);
 
+       } else
 
+               size = GET_MODE_SIZE(mode);
 
+
 
+       return (size > GET_MODE_SIZE(SImode)); // > 1 word : is this okay?
 
+       // The idea is to pass everything larger than an int by reference (or
 
+       // on the stack)
 
+}
 
+*/
 
+
 
+/*
+/*
+ * Code taken from m68k ...
+ * Code taken from m68k ...
+ */
+ */
+static bool
+static bool
+zip_can_eliminate(int from, int to)
+zip_can_eliminate(int from, int to)
Line 1416... Line 1369...
+               return !cfun->machine->fp_needed;
+               return !cfun->machine->fp_needed;
+       return true;
+       return true;
+}
+}
+
+
+/*
+/*
+static bool
 
+zip_must_pass_in_stack(enum machine_mode mode, const_tree type)
 
+{
 
+       if (mode == BLKmode) {
 
+               return true;
 
+       } if (type == NULL) {
 
+               return false;
 
+       } return AGGREGATE_TYPE_P(type);
 
+}
 
+*/
 
+
 
+/*
 
+static void
+static void
+zip_basic_check(void)
+zip_basic_check(void)
+{
+{
+       gcc_assert(mode_base_align[SImode]==4);
+       gcc_assert(mode_base_align[SImode]==4);
+       if ((BITS_PER_UNIT != 32)
+       if ((BITS_PER_UNIT != 32)
Line 1469... Line 1410...
+       return (size + UNITS_PER_WORD - 1)/UNITS_PER_WORD;
+       return (size + UNITS_PER_WORD - 1)/UNITS_PER_WORD;
+}
+}
+
+
+/* pushed in function prologue */
+/* pushed in function prologue */
+/*
+/*
+static void
 
+zip_setup_incoming_varargs(CUMULATIVE_ARGS *cum, enum machine_mode mode,
 
+               tree type, int *pretend_size, int no_rtl) {
 
+       if (no_rtl)
 
+               return;
 
+
 
+       gcc_assert(mode != BLKmode);
 
+
 
+       if (*cum < (ZIP_LAST_ARG_REGNO+1)) {
 
+               int size = ZIP_FIRST_ARG_REGNO + ZIP_NUM_ARGS_REGS - *cum;
 
+               rtx     regblock;
 
+               int     offset = (*cum - ZIP_FIRST_ARG_REGNO) * UNITS_PER_WORD;
 
+               regblock = gen_rtx_MEM(BLKmode,
 
+                       plus_constant(arg_pointer_rtx, offset));
 
+               move_block_from_reg(*cum, regblock, size);
 
+               *pretend_size = size * UNITS_PER_WORD;
 
+       }
 
+
 
+       if (targetm.calls.strict_argument_naming(cum))
 
+               *cum = *cum + zip_num_arg_regs(mode, type);
 
+}
 
+*/
 
+
 
+/*
 
+static int
+static int
+zip_arg_partial_bytes(CUMULATIVE_ARGS *cum, enum machine_mode mode,
+zip_arg_partial_bytes(CUMULATIVE_ARGS *cum, enum machine_mode mode,
+               tree type, bool name ATTRIBUTE_UNUSED) {
+               tree type, bool name ATTRIBUTE_UNUSED) {
+       int     words;
+       int     words;
+       unsigned int    regs = zip_num_arg_regs(mode, type);
+       unsigned int    regs = zip_num_arg_regs(mode, type);
Line 1546... Line 1463...
+               return NULL_RTX;
+               return NULL_RTX;
+       return
+       return
+               gen_rtx_REG(mode, (*cum)+1);
+               gen_rtx_REG(mode, (*cum)+1);
+}
+}
+
+
 
+#ifdef HAVE_cc0
+/* NOTICE_UPDATE_CC sends us here
+/* NOTICE_UPDATE_CC sends us here
+ */
+ */
+void
+void
+zip_update_cc_notice(rtx exp, rtx_insn *insn)
+zip_update_cc_notice(rtx exp, rtx_insn *insn)
+{
+{
 
+#error "The CC0 code was supposed to be removed"
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       enum    attr_ccresult  ccr;
+       enum    attr_ccresult  ccr;
+       enum    attr_conditional  conditionally_executed;
+       enum    attr_conditional  conditionally_executed;
+
+
+       // The default is that nothing has changed.
+       // The default is that nothing has changed.
Line 1693... Line 1612...
+//             ... or value2.  This is the common ZipCPU case.
+//             ... or value2.  This is the common ZipCPU case.
+//
+//
+//             then delete the compare.
+//             then delete the compare.
+//
+//
+}
+}
 
+#else
 
+
 
+void   zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
 
+               bool preserve_op0)
 
+{
 
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
 
+
 
+       if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
 
+       if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
 
+       if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
 
+       if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
 
+
 
+       if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
 
+               rtx tem = *op0;
 
+               *op0 = *op1;
 
+               *op1 = tem;
 
+               *code = (int)swap_condition((enum rtx_code)*code);
 
+       }
 
+
 
+       if ((*code == LE)||(*code == LEU)||(*code == GTU)) {
 
+               int offset = 1; // (*code == GTU) ? 1 : -1;
 
+               bool    swap = false;
 
+
 
+               if (CONST_INT_P(*op1)) {
 
+                       *op1 = GEN_INT(INTVAL(*op1)+offset);
 
+                       swap = true;
 
+               } else if (REG_P(*op1)) {
 
+                       *op1 = plus_constant(SImode, *op1, offset, true);
 
+                       swap = true;
 
+               } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
 
+                       *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
 
+                               INTVAL(XEXP(*op1,1))+offset);
 
+                       swap = true;
 
+               } if (swap) {
 
+                       if (*code == LE)
 
+                               (*code)= LT;
 
+                       else if (*code == LEU)
 
+                               (*code)= LTU;
 
+                       else // (*code == GTU)
 
+                               (*code) = GEU;
 
+               }
 
+       }
 
+}
 
+
 
+static bool
 
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
 
+       *a = zip_CC;
 
+       *b = INVALID_REGNUM;
 
+       return true;
 
+}
 
+
 
+#endif
+
+
+
+
+/* totally buggy - we can't return pointers to nested functions */
+/* totally buggy - we can't return pointers to nested functions */
+static void
+static void
+zip_asm_trampoline_template(FILE *f) {
+zip_asm_trampoline_template(FILE *f) {
Line 1911... Line 1882...
+                       break;
+                       break;
+#endif
+#endif
+               case SImode:
+               case SImode:
+                       fprintf(stderr, "%s:SI\n", str);
+                       fprintf(stderr, "%s:SI\n", str);
+                       break;
+                       break;
 
+               case CCmode:
 
+                       fprintf(stderr, "%s:CC\n", str);
 
+                       break;
+               case DImode:
+               case DImode:
+                       fprintf(stderr, "%s:DI\n", str);
+                       fprintf(stderr, "%s:DI\n", str);
+                       break;
+                       break;
+               default:
+               default:
+                       fprintf(stderr, "%s:?\n", str);
+                       fprintf(stderr, "%s:?\n", str);
Line 1931... Line 1905...
+               sprintf(buf, "(BAD-RTX-CODE %d)", GET_CODE(x));
+               sprintf(buf, "(BAD-RTX-CODE %d)", GET_CODE(x));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               gcc_assert(0 && "Bad RTX Code");
+               gcc_assert(0 && "Bad RTX Code");
+               return;
+               return;
+       } switch(GET_CODE(x)) { // rtl.def
+       } switch(GET_CODE(x)) { // rtl.def
+       case PARALLEL: zip_debug_print(pfx, lvl, "(PARALLEL");
+       case PARALLEL:
+               debug_rtx(x); break;
+               zip_debug_print(pfx, lvl, "(PARALLEL");
 
+               for(int j=0; j<XVECLEN(x,0);j++)
 
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
 
+               zip_debug_print(pfx, lvl, ")");
 
+               debug_rtx(x);
 
+               break;
+       case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break;
+       case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break;
+       case SEQUENCE: zip_debug_print(pfx, lvl, "(SEQUENCE"); break;
+       case SEQUENCE:
 
+               zip_debug_print(pfx, lvl, "(SEQUENCE");
 
+               for(int j=0; j<XVECLEN(x,0);j++)
 
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
 
+               zip_debug_print(pfx, lvl, ")");
 
+               debug_rtx(x);
 
+               break;
+       case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break;
+       case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break;
+       case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break;
+       case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break;
+       case INSN:
+       case INSN:
+               zip_debug_print(pfx, lvl, "(INSN");
+               zip_debug_print(pfx, lvl, "(INSN");
+               /*
+               /*
Line 2005... Line 1990...
+               zip_debug_rtx_1(pfx, SET_DEST(x),lvl+1);
+               zip_debug_rtx_1(pfx, SET_DEST(x),lvl+1);
+               zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
+               zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
+               zip_debug_print(pfx, lvl, ")");
+               zip_debug_print(pfx, lvl, ")");
+               debug_rtx(x);
+               debug_rtx(x);
+               break;
+               break;
+       case REG:
+       case REG: {
 
+               char buf[25];
+               if (REGNO(x) == zip_PC)
+               if (REGNO(x) == zip_PC)
+                       zip_debug_print(pfx, lvl, "(PC)");
+                       sprintf(buf, "(PC)");
+               else if (REGNO(x) == zip_CC)
+               else if (REGNO(x) == zip_CC)
+                       zip_debug_print(pfx, lvl, "(CC0)");
+                       sprintf(buf, "(CC)");
+               else if (REGNO(x) == zip_SP)
+               else if (REGNO(x) == zip_SP)
+                       zip_debug_print(pfx, lvl, "(SP)");
+                       sprintf(buf, "(SP)");
+               else if (REGNO(x) == zip_FP)
+               else if (REGNO(x) == zip_FP)
+                       zip_debug_print(pfx, lvl, "(REG FP)");
+                       sprintf(buf, "(REG FP)");
+               else if (REGNO(x) == zip_GOT)
+               else if (REGNO(x) == zip_GOT)
+                       zip_debug_print(pfx, lvl, "(REG GBL)");
+                       sprintf(buf, "(REG GBL)");
+               else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
+               else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
+                       zip_debug_print(pfx, lvl, "(REG RTN-VL)");
+                       sprintf(buf, "(REG RTN-VL)");
+               else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
+               else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
+                       zip_debug_print(pfx, lvl, "(REG RTN-AD)");
+                       sprintf(buf, "(REG RTN-AD)");
+               else { char buf[25];
+               else
+               sprintf(buf, "(REG %d)", REGNO(x));
+               sprintf(buf, "(REG %d)", REGNO(x));
+               zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
+               zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
+               } break;
+               } break;
+       case IF_THEN_ELSE: // 51
+       case IF_THEN_ELSE: // 51
+               zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
+               zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
Line 2059... Line 2045...
+               else
+               else
+                       sprintf(buf, "(CONST_INT:? %ld)", INTVAL(x));
+                       sprintf(buf, "(CONST_INT:? %ld)", INTVAL(x));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               } break;
+               } break;
+       case LABEL_REF:
+       case LABEL_REF:
+               { char buf[256], *bp;
+               { char buf[256];
+               sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
+               sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               }
+               }
+               break;
+               break;
+       case SYMBOL_REF:
+       case SYMBOL_REF:
Line 2239... Line 2225...
+       }
+       }
+}
+}
+
+
+
+
+static bool
+static bool
+zip_legitimate_opb(const_rtx x, bool strict)
+zip_legitimate_opb(rtx x, bool strict)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
+
+
+       if (NULL_RTX == x)
+       if (NULL_RTX == x)
+               return false;
+               return false;
+       else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode))
+       else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
 
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
+               return false;
+               return false;
+       else if (REG_P(x)) {
+       } else if ((strict)&&(REG_P(x))) {
+               bool    res;
+               if (REGNO(x)<zip_CC) {
+               // Only insist the register b a valid register if strict is true
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
+               res = (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) != zip_CC));
+                       return true;
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> %s (Reg)\n",
+               } else return false;
+                       (res)?"YES!":"No");
+       } else if (register_operand(x, GET_MODE(x))) {
+               return res;
+               // This also handles subregs
+       } else if ((!strict)&&(SUBREG_P(x))) {
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
+               // Only insist the register b a valid register if strict is true
+               return true;
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Subreg(Reg),recurse)\n");
 
+               return zip_legitimate_opb(XEXP(x,0), strict);
 
+       } else if ((CONST_INT_P(x))
+       } else if ((CONST_INT_P(x))
+               &&(INTVAL(x) >= zip_min_opb_imm)
+               &&(INTVAL(x) >= zip_min_opb_imm)
+               &&(INTVAL(x) <= zip_max_opb_imm)) {
+               &&(INTVAL(x) <= zip_max_opb_imm)) {
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const)\n");
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const) %ld <= %ld <= %ld\n", zip_min_opb_imm, INTVAL(x), zip_max_opb_imm);
+               return true;
+               return true;
 
+       // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
 
+               // return true;
+       } else if (GET_CODE(x) == PLUS) {
+       } else if (GET_CODE(x) == PLUS) {
+               // Is it a valid register?
+               // Is it a valid register?
+               if(!REG_P(XEXP(x,0))) {
+               if ((!strict)&&(!register_operand((rtx)XEXP((rtx)x,0), GET_MODE(x)))) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       return false;
+                       return false;
+               } if ((strict)&&((!is_ZIP_REG(REGNO(XEXP(x,0))))||(REGNO(XEXP(x,0)) == zip_CC))) {
+               } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
 
+                       return false;
+                       return false;
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
+                       // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
+                       // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
+                               // gcc_unreachable();
+                               // gcc_unreachable();
+                       return true;
+                       return true;
+               } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
+               } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
 
+                       ||(GET_CODE(XEXP(x, 1)) == CODE_LABEL)
+                       ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
+                       ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
+                       // While we can technically support this, the problem
+                       // While we can technically support this, the problem
+                       // is that the symbol address could be anywhere, and we
+                       // is that the symbol address could be anywhere, and we
+                       // have no way of recovering if it's outside of our
+                       // have no way of recovering if it's outside of our
+                       // 14 allowable bits.
+                       // 14 allowable bits.
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
+                       return false;
+                       return false;
+               }
+               }
+               // if ((GET_CODE(XEXP(x, 1)) == MINUS)
 
+               //      &&((GET_CODE(XEXP(XEXP(x,1),0)) == LABEL_REF)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),0)) == SYMBOL_REF))
 
+               //      &&((GET_CODE(XEXP(XEXP(x,1),1)) == LABEL_REF)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
 
+               //              ||(GET_CODE(XEXP(XEXP(x,1),1)) == SYMBOL_REF))
 
+               //      &&((GET_CODE(XEXP(XEXP(x,1),0)))
 
+               //              == (GET_CODE(XEXP(XEXP(x,1),1))))) {
 
+               //      if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (lbl-lbl+reg)\n");
 
+               //      return true;
 
+               //}
 
+       }
+       }
+
+
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
+       if (dbg) zip_debug_rtx(x);
+       if (dbg) zip_debug_rtx(x);
+       return false;
+       return false;
Line 2317... Line 2292...
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
+       if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
+       if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
+
+
+       if (NULL_RTX == x)
+       if (!zip_legitimate_opb(x, strict))
+               return false;
 
+       else if (REG_P(x)) {
 
+               // Only insist the register b a valid register if strict is true
 
+               if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> YES! (Reg)\n");
 
+               return (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) !=zip_CC));
 
+       } else if (GET_CODE(x) == PLUS) {
 
+               // if (GET_CODE(XEXP(x,0))==PLUS) {
 
+               // return (zip_legitimate_opb(XEXP(x,0), strict))
 
+               // &&(zip_const_address_operand(XEXP(x,0)));
 
+               // }
 
+               // Is it a valid register?
 
+               if(GET_CODE(XEXP(x,0)) != REG) {
 
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (No reg in +%s)\n",
 
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
 
+                       return false;
+                       return false;
+               } if ((strict)&&
+       else if ((GET_CODE(x)==PLUS)&&(CONST_INT_P(XEXP(x,1)))) {
+                       ((!is_ZIP_REG(REGNO(XEXP(x,0))))
+               if ((INTVAL(XEXP(x, 1)) > zip_max_mov_offset)
+                       ||(REGNO(XEXP(x,0)) == zip_CC))) {
+                       ||(INTVAL(XEXP(x, 1)) < zip_min_mov_offset)) {
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> NO! (reg+int), int out of bounds: %d\n", INTVAL(XEXP(x,1)));
+                       return false;
+                       return false;
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
 
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_mov_offset)
 
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_mov_offset)) {
 
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> YES! (reg+int)\n");
 
+                       return true;
 
+               }
+               }
+       }
+       }
+
+
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No\n");
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> Yes\n");
+       if (dbg) zip_debug_rtx(x);
+       if (dbg) zip_debug_rtx(x);
+       return false;
+       return true;
+}
+}
+
+
+int
+int
+zip_pd_mov_operand(rtx op)
+zip_pd_mov_operand(rtx op)
+{
+{
Line 2411... Line 2367...
+zip_pd_opb_operand(rtx op)
+zip_pd_opb_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
+       return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
+zip_ct_address_operand(rtx op)
+zip_ct_address_operand(rtx op)
+{
+{
Line 2518... Line 2474...
+       fprintf(stream, "\t.equ ");
+       fprintf(stream, "\t.equ ");
+       assemble_name(stream, value);
+       assemble_name(stream, value);
+       fputc('\n', stream);
+       fputc('\n', stream);
+}
+}
+
+
+/*
 
+bool   zip_load_address_lod(rtx regrx, rtx memrx) {
 
+       fprintf(stderr, "ZIP-LOAD-ADDRESS-LOD\n");
 
+       if (!MEM_P(memrx))
 
+               return false;
 
+       if (GET_CODE(regrx) != REG)
 
+               return false;
 
+       enum    rtx_code ic = GET_CODE(memrx);
 
+       if ((ic == SYMBOL_REF)
 
+               ||(ic == CODE_LABEL)
 
+               ||(ic == LABEL_REF)) {
 
+               if (can_create_pseudo_p()) {
 
+                       rtx scratch_reg;
 
+                       scratch_reg = gen_rtx_SCRATCH(SImode);
 
+                       emit_insn(gen_movsi_ldi(scratch_reg, XEXP(memrx, 0)));
 
+                       emit_insn(gen_movsi_lod(regrx, scratch_reg));
 
+                       return true;
 
+               } else return false;
 
+       } else return false;
 
+}
 
+
 
+bool   zip_load_address_sto(rtx memrx, rtx regrx) {
 
+       fprintf(stderr,  "CHECKING-IN-W/ZIP_LOAD_ADDRESS_STORE\n");
 
+       if (!MEM_P(memrx))
 
+               return false;
 
+       if (GET_CODE(regrx) != REG)
 
+               return false;
 
+       enum    rtx_code ic = GET_CODE(memrx);
 
+       if ((ic == SYMBOL_REF)
 
+               ||(ic == CODE_LABEL)
 
+               ||(ic == LABEL_REF)) {
 
+               if (can_create_pseudo_p()) {
 
+                       rtx scratch_reg;
 
+                       scratch_reg = gen_rtx_SCRATCH(SImode);
 
+                       emit_insn(gen_movsi_ldi(scratch_reg, XEXP(memrx, 0)));
 
+                       emit_insn(gen_movsi_sto(scratch_reg, regrx));
 
+                       return true;
 
+               } else return false;
 
+       } return false;
 
+}
 
+*/
 
+
 
+#define        USE_SUBREG
+#define        USE_SUBREG
+#ifdef USE_SUBREG
+#ifdef USE_SUBREG
+#define        SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
+#define        SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
+#define        SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
+#define        SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
+#else
+#else
+#define        SREG_P(RTX)     false
+#define        SREG_P(RTX)     false
+#define        SMEM_P(RTX)     false
+#define        SMEM_P(RTX)     false
+#endif
+#endif
+
+
+bool   zip_gen_move_rtl(rtx dst, rtx src) {
 
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
 
+
 
+       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE\n");
 
+       if (dbg) zip_debug_rtx_pfx("FROM: ", src);
 
+       if (dbg) zip_debug_rtx_pfx("TO  : ", dst);
 
+       if (dbg) fprintf(stderr, "PSEUDOs: %s\n", can_create_pseudo_p()?"true":"false");
 
+       if (((REG_P(dst))||(SREG_P(dst)))
 
+                       &&((REG_P(src))||(SREG_P(src)))) {
 
+               // First type of move... register to register
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG -- EMIT\n");
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
 
+               // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src));
 
+               emit_insn(gen_movsi_reg(dst, src));
 
+       } else if ((MEM_P(dst))&&(MEM_P(XEXP(dst,0)))) {
 
+               // An indirect store, (mem (mem (addr .))) = whatever ...
 
+               if (can_create_pseudo_p()) {
 
+                       rtx     tmp = gen_reg_rtx(Pmode);
 
+                       zip_gen_move_rtl(tmp, XEXP(dst,0));
 
+                       // mark_reg_pointer(tmp,0);
 
+                       zip_gen_move_rtl(gen_rtx_MEM(GET_MODE(src), tmp), src);
 
+               } else {
 
+                       fprintf(stderr, "ZIP:Cannot move into mem w/o pseudo\n");
 
+                       return false;
 
+               }
 
+       } else if ((MEM_P(src))&&(MEM_P(XEXP(src,0)))) {
 
+               // If this is an indirect load, Rx = (mem (mem (addr)))
 
+               if (can_create_pseudo_p()) {
 
+                       rtx     tmp = gen_reg_rtx(Pmode);
 
+                       zip_gen_move_rtl(tmp, XEXP(src,0));
 
+                       // mark_reg_pointer(tmp,0);
 
+                       zip_gen_move_rtl(dst, gen_rtx_MEM(GET_MODE(src), tmp));
 
+               } else {
 
+                       fprintf(stderr, "ZIP: Cannot move from mem(mem(ptr)) w/o pseudo\n");
 
+                       return false;
 
+               }
 
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src)==PLUS)
 
+                       &&(REG_P(XEXP(src,0)))
 
+                       &&(CONST_INT_P(XEXP(src,1)))) {
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
 
+               // Second type of move... register plus offset to register
 
+               if ((INTVAL(XEXP(src, 1)) <= zip_max_mov_offset)
 
+                       &&(INTVAL(XEXP(src, 1)) >= zip_min_mov_offset)) {
 
+                       // The offset is within bounds
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG+OFF -- EMIT\n");
 
+                       emit_insn(gen_movsi_reg_off(dst, XEXP(src,0),XEXP(src,1)));
 
+               } else if (can_create_pseudo_p()) {
 
+                       // The offset is out of bounds, get a new register and
 
+                       // generate an add instruction to split this up.
 
+                       rtx     tmp = gen_reg_rtx(GET_MODE(XEXP(src,0)));
 
+
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LDI\n");
 
+                       emit_insn(gen_movsi_ldi(tmp, XEXP(src,1)));
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/ADD\n");
 
+                       emit_insn(gen_addsi3(tmp, tmp, XEXP(src,0)));
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/DST\n");
 
+                       emit_insn(gen_movsi_reg(dst, tmp));
 
+               } else {
 
+                       fprintf(stderr, "ZIP: Cannot move a(r),b w/o pseudo for out of bounds a\n");
 
+                       return false;
 
+               }
 
+       } else if ((MEM_P(dst))&&(MEM_P(src))) {
 
+               rtx     tmp;
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/MEM/MEM\n");
 
+               if (can_create_pseudo_p()) {
 
+                       tmp = gen_reg_rtx(GET_MODE(src));
 
+                       emit_insn(gen_movsi(tmp, src));
 
+                       emit_insn(gen_movsi(dst, tmp));
 
+               } else {
 
+                       fprintf(stderr, "ZIP: Cannot move mem(A) to mem(B) w/o pseudo\n");
 
+                       return false;
 
+               }
 
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(MEM_P(src))) {
 
+               // Memory load
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD\n");
 
+               if (zip_legitimate_opb(XEXP(src, 0), false)) {
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/SIMPLE-LOD(ADDR)\n");
 
+                       if (dbg) zip_debug_rtx_pfx("Smple-Addr: ", src);
 
+                       emit_insn(gen_movsi_lod(dst, src));
 
+               } else if (zip_const_address_operand(XEXP(src,0))) {
 
+                       if (can_create_pseudo_p()) {
 
+                               rtx     tmp;
 
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR)\n");
 
+                               tmp = gen_reg_rtx(Pmode);
 
+                               emit_insn(gen_movsi_ldi(tmp, XEXP(src,0)));
 
+                               emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),tmp)));
 
+                       } else {
 
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR,SELF)\n");
 
+                               emit_insn(gen_movsi_ldi(dst, XEXP(src,0)));
 
+                               emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),dst)));
 
+                       }
 
+               } else {
 
+                       internal_error("%s", "ZIP/No usable load\n");
 
+               }
 
+       } else if ((MEM_P(dst))&&((REG_P(src))||(SREG_P(src)))) {
 
+               // Memory store
 
+               // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src));
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO\n");
 
+               if (zip_legitimate_opb(XEXP(dst, 0), false)) {
 
+                       // If it's a legitimate address already, do nothing mor
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO(Legit Addr)--EMIT\n");
 
+                       // if (REG_P(XEXP(dst,0)))
 
+                               // mark_reg_pointer(XEXP(dst,0),0);
 
+                       // else if ((GET_CODE(XEXP(dst,0))==PLUS)
 
+                                       // &&(REG_P(XEXP(XEXP(dst,0),0))))
 
+                               // mark_reg_pointer(XEXP(XEXP(dst,0),0),0);
 
+                       emit_insn(gen_movsi_sto(dst, src));
 
+               } else if (zip_const_address_operand(XEXP(dst,0))) {
 
+                       rtx     tmp;
 
+
 
+                       if (can_create_pseudo_p()) {
 
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO(Const Addr,Reg) -- EMIT\n");
 
+                               // Otherwise we need to load the memory address
 
+                               // into a register
 
+                               tmp = gen_reg_rtx(Pmode);
 
+                               // mark_reg_pointer(tmp,0);
 
+                               emit_insn(gen_movsi_ldi(tmp, XEXP(dst,0)));
 
+                               //
 
+                               // Then we can do our load
 
+                               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO -- emit\n");
 
+                               emit_insn(gen_movsi_sto(gen_rtx_MEM(GET_MODE(src), tmp), src));
 
+                       } else {
 
+                               fprintf(stderr, "Cannot move src -> mem(dst) w/o pseudo\n");
 
+                               return false;
 
+                       }
 
+               } else if (can_create_pseudo_p())
 
+                       internal_error("%s", "ZIP/No usable store\n");
 
+               else {
 
+                       fprintf(stderr, "ZIP/Unanticipated store problem\n");
 
+                       return false;
 
+               }
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO -- DONE\n");
 
+       } else if ((MEM_P(dst))&&((CONST_INT_P(src))||(GET_CODE(src)==SYMBOL_REF))) {
 
+               // Store a constant into memory
 
+               rtx     tmp;
 
+
 
+               if (can_create_pseudo_p()) {
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->MEM\n");
 
+                       // Load the source constant into a register first
 
+                       tmp = gen_reg_rtx((GET_MODE(src)==VOIDmode)?GET_MODE(dst):GET_MODE(src));
 
+                       emit_insn(gen_movsi_ldi(tmp,src));
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->REG->MEM -- RECURSE\n");
 
+
 
+                       // Then do a normal move, recursing to handle memory
 
+                       // properly
 
+                       zip_gen_move_rtl(dst, tmp);
 
+                       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->MEM -- DONE\n");
 
+               } else {
 
+                       fprintf(stderr, "ZIP/Cannot store constant into mem w/o pseudo\n");
 
+                       return false;
 
+               }
 
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(CONST_INT_P(src))) {
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
 
+               // Load a constant into a register
 
+               // The assembler really takes care of all of this, since
 
+               // the assembler will split the constant if it doesn't fit
 
+               // into a single instruction.
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/CONST->REG\n");
 
+               // if ((GET_MODE(dst)==VOIDmode)&&(GET_MODE(src)==VOIDmode))
 
+                       // PUT_MODE(dst,SImode);
 
+               emit_insn(gen_movsi_ldi(dst, src));
 
+       } else if ((REG_P(dst))&&
 
+                       ((LABEL_P(src))
 
+                       ||(GET_CODE(src)==SYMBOL_REF)
 
+                       ||(GET_CODE(src)==LABEL_REF))) {
 
+               // Load a constant into a register
 
+               // The assembler really takes care of all of this, since
 
+               // the assembler will split the constant if it doesn't fit
 
+               // into a single instruction.
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL->REG\n");
 
+               emit_insn(gen_movsi_ldi(dst, src));
 
+       } else if ((REG_P(dst))&&
 
+                       ((GET_CODE(src)==PLUS)
 
+                       &&((GET_CODE(XEXP(src,0))==SYMBOL_REF)
 
+                               ||(GET_CODE(XEXP(src,0))==LABEL_REF))
 
+                       &&(CONST_INT_P(XEXP(src,1))))) {
 
+               if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL+OFFSET->REG\n");
 
+               if ((INTVAL(XEXP(src,1))>=zip_min_mov_offset)
 
+                       &&(INTVAL(XEXP(src,1))<=zip_max_mov_offset)) {
 
+                       emit_insn(gen_movsi_ldi(dst, XEXP(src,1)));
 
+                       emit_insn(gen_movsi_reg_off(dst, dst, XEXP(src,1)));
 
+               } else if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(Pmode);
 
+                       emit_insn(gen_movsi_ldi(tmp, XEXP(src,1)));
 
+                       emit_insn(gen_movsi_ldi(dst, src));
 
+                       emit_insn(gen_addsi3(dst,dst,tmp));
 
+                       return true;
 
+               } else {
 
+                       fprintf(stderr, "Cannot move LABEL+OFFSET -> dst w/o pseudo\n");
 
+                       return false;
 
+               }
 
+       } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src) == CONST)) {
 
+               // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
 
+               zip_gen_move_rtl(dst, XEXP(src,0));
 
+       } else if (SMEM_P(dst)) {
 
+               rtx     addr = XEXP(XEXP(dst,0),0);
 
+               if (REG_P(addr)) {
 
+                       zip_gen_move_rtl(
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addr,
 
+                                       SUBREG_BYTE(dst),false)),src);
 
+               } else if ((GET_CODE(addr)==PLUS)
 
+                               &&(REG_P(XEXP(addr,0)))
 
+                               &&(CONST_INT_P(XEXP(addr,1)))) {
 
+                       rtx addreg = XEXP(addr,0);
 
+                       zip_gen_move_rtl(
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addreg,
 
+                                       INTVAL(XEXP(addr,1))+SUBREG_BYTE(dst),
 
+                                       false)),src);
 
+               } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n");
 
+       } else if (SMEM_P(src)) {
 
+               rtx     addr = XEXP(XEXP(src,0),0);
 
+               if (REG_P(addr)) {
 
+                       zip_gen_move_rtl(dst,
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addr,
 
+                                       SUBREG_BYTE(src),false)));
 
+               } else if ((GET_CODE(addr)==PLUS)
 
+                               &&(REG_P(XEXP(addr,0)))
 
+                               &&(CONST_INT_P(XEXP(addr,1)))) {
 
+                       rtx addreg = XEXP(addr,0);
 
+                       zip_gen_move_rtl(dst,
 
+                               gen_rtx_MEM(SImode, plus_constant(Pmode,addreg,
 
+                                       INTVAL(XEXP(addr,1))+SUBREG_BYTE(src),
 
+                                       false)));
 
+               } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n");
 
+       } else {
 
+               fprintf(stderr, "ZIP/No usable move\n");
 
+               zip_debug_rtx_pfx("TO  : ", dst);
 
+               zip_debug_rtx_pfx("FROM: ", src);
 
+               debug_rtx(dst);
 
+               debug_rtx(src);
 
+               return false;
 
+       }
 
+       if (dbg) fprintf(stderr, "ZIP-GEN-MOVE -- DONE\n");
 
+       return true;
 
+}
 
+
 
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
+       if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
+       if (dbg) zip_debug_rtx_pfx("REG", dst);
+       if (dbg) zip_debug_rtx_pfx("REG", dst);
Line 3030... Line 2707...
+               rv += 2;
+               rv += 2;
+       return rv;
+       return rv;
+}
+}
+
+
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
+
 
+static bool    zip_cannot_modify_jumps_p(void) {
+static bool    zip_cannot_modify_jumps_p(void) {
+       // Let's try their suggested approach, keeping us from modifying jumps
+       // Let's try their suggested approach, keeping us from modifying jumps
+       // after reload.  This should also allow our peephole2 optimizations
+       // after reload.  This should also allow our peephole2 optimizations
+       // to adjust things back to what they need to be if necessary.
+       // to adjust things back to what they need to be if necessary.
+       return (reload_completed || reload_in_progress);
+       return (reload_completed || reload_in_progress);
+}
+}
 
+
 
+rtx_insn       *zip_ifcvt_info;
 
+
 
+void
 
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
 
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
 
+       if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
 
+       if (*true_expr) switch(GET_CODE(*true_expr)) {
 
+               case LE:
 
+               case GTU:
 
+               case GEU:
 
+               case LEU:
 
+                       if (dbg) fprintf(stderr, "TRUE, missing expr\n");
 
+                       if (dbg) zip_debug_rtx(*true_expr);
 
+                       *true_expr = NULL_RTX;
 
+                       break;
 
+               default: // LT, GT, GTE, LTU, NE, EQ
 
+                       break;
 
+       }
 
+
 
+       if (*false_expr) switch(GET_CODE(*false_expr)) {
 
+               case LE:
 
+               case GTU:
 
+               case GEU:
 
+               case LEU:
 
+                       if (dbg) fprintf(stderr, "FALSE, missing expr\n");
 
+                       if (dbg) zip_debug_rtx(*false_expr);
 
+                       *false_expr = NULL_RTX;
 
+               default:
 
+                       break;
 
+       }
 
+       if ((dbg)&&((!*true_expr)||(!*false_expr)))
 
+               fprintf(stderr, "IFCVT-MODIFY-TESTS -- FAIL\n");
 
+}
 
+
 
+void
 
+zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
 
+/*
 
+       fprintf(stderr, "IFCVT -- CANCEL\n");
 
+       zip_ifcvt_info = NULL;
 
+*/
 
+}
 
+
 
+void
 
+zip_ifcvt_modify_final(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
 
+/*
 
+rtx_insn *insn;
 
+FOR_BB_INSNS(ceinfo->test_bb, insn)
 
+       fprintf(stderr, "IFCVT -- FINAL\n");
 
+       zip_debug_rtx_pfx("FINAL-TEST-BB", insn);
 
+       zip_ifcvt_info = NULL;
 
+*/
 
+}
 
+
 
+void
 
+zip_ifcvt_machdep_init(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
 
+/*
 
+       zip_ifcvt_info = NULL;
 
+       rtx_insn *insn, *ifinsn = NULL;
 
+       FOR_BB_INSNS(ceinfo->test_bb, insn) {
 
+               rtx     p;
 
+               p = single_set(insn);
 
+               if (!p) continue;
 
+               if (SET_DEST(p)==pc_rtx) {
 
+                       ifinsn = insn;
 
+               }
 
+               if (!REG_P(SET_DEST(p)))
 
+                       continue;
 
+               if (GET_MODE(SET_DEST(p))!=CCmode)
 
+                       continue;
 
+               if (REGNO(SET_DEST(p))!=zip_CC)
 
+                       continue;
 
+               zip_ifcvt_info = insn;
 
+       }
 
+
 
+       if (zip_ifcvt_info)
 
+               zip_debug_rtx_pfx("PUTATIVE-CMP",zip_ifcvt_info);
 
+       if (ifinsn)
 
+               zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
 
+*/
 
+}
 
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-04-01 06:33:55.090614401 -0400
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-04-04 18:41:58.074920257 -0400
@@ -0,0 +1,3898 @@
@@ -0,0 +1,3983 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   gcc/config/zip/zip.h
+// Filename:   gcc/config/zip/zip.h
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 5677... Line 5435...
+ * a byproduct of other activity as well as those that explicitly set (cc0).
+ * a byproduct of other activity as well as those that explicitly set (cc0).
+ *
+ *
+ * ZipCPU --- We need this, as not all expressions set (cc0).
+ * ZipCPU --- We need this, as not all expressions set (cc0).
+ *
+ *
+ */
+ */
 
+#ifdef HAVE_cc0
+#define        NOTICE_UPDATE_CC(EXP, INSN)     zip_update_cc_notice(EXP, INSN)
+#define        NOTICE_UPDATE_CC(EXP, INSN)     zip_update_cc_notice(EXP, INSN)
 
+#endif
+
+
+
+
+/* 17.15.2 Representation of condition codes using registers */
+/* 17.15.2 Representation of condition codes using registers */
+/* ... which the ZipCPU doesn't have.  The ZipCPU has a CC0 register, and hence
+/* ... which the ZipCPU doesn't have.  The ZipCPU has a CC0 register, and hence
+ * this section isn't supposed to apply.
+ * this section isn't supposed to apply.
+ */
+ */
+
+
+/* SELECT_CC_MODE(op, x, y)
+/* SELECT_CC_MODE(op, x, y) ... On many machines, the condition code may be
 
+ * produced by other instructions than compares, for example the branch can use
 
+ * directyl the condition code set by a subtract instruction.  However, on some
 
+ * machines when the condition code is set this way some bits (such as the
 
+ * overflow bit) are not set in the same way as a test instruction, so that a
 
+ * different branch instruction must be used for some conditional branches.
 
+ * When this happens, use the machinemode of the condition code register to
 
+ * record different formats of the condition code register.  Modes can also be
 
+ * used to reccord which compare instruction (e.g. a signed or an unsigned
 
+ * comparison) produced the condition codes.
 
+ *
 
+ * If other modes than CCmode are required, add them to 'machine-modes.def' and
 
+ * define SELECT_CC_MODE to choose a mode given an operand of a compare.  This
 
+ * is needed because the modes have to be chosen not only during RTL generation
 
+ * but also, for example, by instruction combination.  The result of
 
+ * SELECT_CC_MODE should be consistent with the mode used in the patterns; ...
 
+ *
 
+ * ZipCPU ... We have only one CC Mode, so we'll use the CCmode defined in
 
+ * machine-modes.def and should be fine with it.  Hence, this doesn't need
 
+ * to be defined.
+ */
+ */
+
+
+/* TARGET_CANONICALIZE_COMPARISON(int,rtx *, rtx *, bool) ... On some machines
+/* TARGET_CANONICALIZE_COMPARISON(int,rtx *, rtx *, bool) ... On some machines
+ * (such as the ZipCPU) not all possible comparisons are defined, but you can
+ * (such as the ZipCPU) not all possible comparisons are defined, but you can
+ * convert an invalid comparison into a valid one.  For example, the Alpha
+ * convert an invalid comparison into a valid one.  For example, the Alpha
Line 5715... Line 5494...
+ * our comparisons successfully.
+ * our comparisons successfully.
+ *
+ *
+ * The only problem is ... this hook appears to only be called on non-CC0
+ * The only problem is ... this hook appears to only be called on non-CC0
+ * machines.  Hence, defining it hasn't done anything for us.
+ * machines.  Hence, defining it hasn't done anything for us.
+ */
+ */
+// #define     TARGET_CANONICALIZE_COMPARISON  zip_canonicalize_comparison
+#define        TARGET_CANONICALIZE_COMPARISON  zip_canonicalize_comparison
 
+
 
+/* REVERSIBLE_CC_MODE(MODE) ... A C expression whose value is one if it is
 
+ * always safe to reverse a comparison whose mode is MODE.  If SELECT_CC_MODE
 
+ * can ever return MODE for a floating-point inequality comparison, than
 
+ * REVERSIBLE_CC_MODE(MODE) must be zero.
 
+ *
 
+ * You need not define this macro if it would always return zero or if the
 
+ * floating-point format is anything other than IEEE_FLOAT_FORMAT.  For example,
 
+ * here ...
 
+ *
 
+ * ZipCPU -- We'll always return zero, so this need not be defined.
 
+ */
 
+
 
+/* REVERSE_CONDITION(CODE,MODE) ... A C expression whose value is reversed
 
+ * condition code of thecode for comparison done in CC_MODE MODE.  This macro
 
+ * is used only in case REVERSIBLE_CC_MODE(MODE) is nonzero. ...
 
+ *
 
+ * ZipCPU ... Since REVERSIBLE_CC_MODE(MODE) will always be zero, we'll leave
 
+ * this undefined.
 
+ */
 
+
 
+/* bool TARGET_FIXED_CONDITION_CODE_REGS(int *, int *) ... On targets which do
 
+ * not use (cc0), and which use a hard register rather than a pseudo-register
 
+ * to hold condition codes, the regular CSE passes are often not able to
 
+ * identify cases in which the hard register is set to a common value.  Use this
 
+ * hook to enable a small pass which optimizes such cases.  This hook should
 
+ * return true to enable this pass, and it should set the integers to which its
 
+ * arguments point to the hard register numbers used for condition codes.  When
 
+ * there is only one such register, as is true on most systems, the integer
 
+ * pointed to by p2 should  be set to INVALID_REGNUM.
 
+ *
 
+ * The default version of this hook returns false.
 
+ *
 
+ * ZipCPU --- I like the idea of enabling optimizations.  Let's return
 
+ * something other than false.
 
+ */
 
+#define        TARGET_FIXED_CONDITION_CODE_REGS        zip_fixed_condition_code_regs
 
+
 
+/* machine_mode TARGET_CC_MODES_COMPATIBLE(M1,M2) .. On targets which use
 
+ * multiple condition code modes in class MODE_CC, it is sometimes the case
 
+ * that a comparison can be validly done in more than one mode.  On such a
 
+ * system, define this target hook to take two mode arguments and to return a
 
+ * mode in which both comparisons may be validly done.  If there is no such
 
+ * mode, return VOIDmode.
 
+ *
 
+ * The default version of this hook checks whether the modes are the same.  If
 
+ * they are, it returns that mode.  If they are different, it returns VOIDmode.
 
+ *
 
+ * ZipCPU--Given that we only have the one CCmode, the default definition works
 
+ * well enough for us.
 
+ */
 
+
 
+/* unsigned int TARGET_FLAGS_REGNUM ... If the target has a dedicated flags
 
+ * register, and it needs to use the post-reload comparison elimination pass,
 
+ * then this value should be set appropriately.
 
+ *
 
+ * ZipCPU---Looks like we can set this easily enough without any problems.
 
+ */
 
+#undef TARGET_FLAGS_REGNUM
 
+#define        TARGET_FLAGS_REGNUM     zip_CC
+
+
+/* 17.16 Relative costs of operations */
+/* 17.16 Relative costs of operations */
+
+
+
+
+// #define     REGISTER_MOVE_COST(MODE,FROM,TO)        ((MODE==DImode)||(MODE==DFmode))?4:2
+// #define     REGISTER_MOVE_COST(MODE,FROM,TO)        ((MODE==DImode)||(MODE==DFmode))?4:2
Line 6416... Line 6255...
+ * or FALSE to a null pointer if the tests cannot be converted.
+ * or FALSE to a null pointer if the tests cannot be converted.
+ *
+ *
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * execution and conditional testing capabilities.
+ * execution and conditional testing capabilities.
+ */
+ */
+// #warning "Need to come back to this."
+#define        IFCVT_MODIFY_TESTS(CI,TR,FL)    zip_ifcvt_modify_tests(CI,&TR,&FL)
+
+
+/* IFCVT_MODIFY_MULTIPLE_TESTS(CEINFO, BB, TRUE, FALSE) ... Like
+/* IFCVT_MODIFY_MULTIPLE_TESTS(CEINFO, BB, TRUE, FALSE) ... Like
+ * IFCVT_MODIFY_TESTS, but used when converting more complicated if-statements
+ * IFCVT_MODIFY_TESTS, but used when converting more complicated if-statements
+ * into conditions combined by and and or operations.  BB contains the basic
+ * into conditions combined by and and or operations.  BB contains the basic
+ * block that contains the test that is currently being processed and about to
+ * block that contains the test that is currently being processed and about to
Line 6429... Line 6268...
+ *
+ *
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * execution and conditional testing capabilities.
+ * execution and conditional testing capabilities.
+ */
+ */
+// #warning "Need to come back to this."
+// #warning "Need to come back to this."
 
+#define        IFCVT_MODIFY_MULTIPLE_TESTS(CI,BB,TR,FL) TR=NULL_RTX
+
+
+
+
+/* IFCVT_MODIFY_INSN(CEINFO, PATTERN, INSN) ... A C expression to modify the
+/* IFCVT_MODIFY_INSN(CEINFO, PATTERN, INSN) ... A C expression to modify the
+ * PATTERN of an INSN that is to be converted to conditional execution format.
+ * PATTERN of an INSN that is to be converted to conditional execution format.
+ * CEINFO points to a data structure, struct ce_if_block, which contains
+ * CEINFO points to a data structure, struct ce_if_block, which contains
Line 6453... Line 6293...
+ *
+ *
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * execution and conditional testing capabilities.
+ * execution and conditional testing capabilities.
+ */
+ */
+// #warning "Need to come back to this."
+// #warning "Need to come back to this."
 
+#define        IFCVT_MODIFY_FINAL(CEINFO)      zip_ifcvt_modify_final(CEINFO)
+
+
+
+
+/* IFCVT_MODIFY_CANCEL(CEINFO) ... A C expression to cancel any machine
+/* IFCVT_MODIFY_CANCEL(CEINFO) ... A C expression to cancel any machine
+ * dependent modifications in converting code to conditional execution.  The
+ * dependent modifications in converting code to conditional execution.  The
+ * involved basic blocks can be found in the struct ce_if_block structure that
+ * involved basic blocks can be found in the struct ce_if_block structure that
Line 6465... Line 6306...
+ *
+ *
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * execution and conditional testing capabilities.
+ * execution and conditional testing capabilities.
+ */
+ */
+// #warning "Need to come back to this."
+// #warning "Need to come back to this."
 
+#define        IFCVT_MODIFY_CANCEL(CEINFO)     zip_ifcvt_modify_cancel(CEINFO)
+
+
+
+
+/* IFCVT_MACHDEP_INIT(CEINFO) ... A C expression to initialize any machine
+/* IFCVT_MACHDEP_INIT(CEINFO) ... A C expression to initialize any machine
+ * specific data for if-conversion of the if-block in the CEINFO block structure
+ * specific data for if-conversion of the if-block in the CEINFO block structure
+ * that is pointed by CEINFO.
+ * that is pointed by CEINFO.
Line 6476... Line 6318...
+ *
+ *
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
+ * execution and conditional testing capabilities.
+ * execution and conditional testing capabilities.
+ */
+ */
+// #warning "Need to come back to this."
+// #warning "Need to come back to this."
 
+#define        IFCVT_MACHDEP_INIT(CEINFO)      zip_ifcvt_machdep_init(CEINFO)
+
+
+
+
+/* TARGET_MACHINE_DEPENDENT_REORG(VOID) ... If non-null, this hook performs a
+/* TARGET_MACHINE_DEPENDENT_REORG(VOID) ... If non-null, this hook performs a
+ * target specific pass over the instruction stream.  The compiler will run it
+ * target specific pass over the instruction stream.  The compiler will run it
+ * at all optimization levels, just before the point at which it normally does
+ * at all optimization levels, just before the point at which it normally does
Line 6941... Line 6784...
+
+
+#endif /* GCC_ZIP_H */
+#endif /* GCC_ZIP_H */
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-01 19:21:20.490611131 -0400
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-06 17:47:12.387591487 -0400
@@ -0,0 +1,2122 @@
@@ -0,0 +1,2262 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+;; Filename:   zip.md
+;; Filename:   zip.md
+;;
+;;
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
Line 7053... Line 6896...
+{
+{
+       return zip_pd_opb_operand(op);
+       return zip_pd_opb_operand(op);
+})
+})
+
+
+(define_predicate "zip_opb_operand_p"
+(define_predicate "zip_opb_operand_p"
+       (match_code "reg,plus,const_int")
+       (match_code "reg,plus,const_int,subreg")
+{
+{
+       return zip_pd_opb_operand(op);
+       return zip_pd_opb_operand(op);
+})
+})
+
+
 
+(define_predicate "zip_opb_immv_p"
 
+       (match_code "const_int")
 
+{
 
+       return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13)));
 
+})
 
+
+(define_predicate "zip_opb_single_operand_p"
+(define_predicate "zip_opb_single_operand_p"
+       (match_code "reg,const_int")
+       (match_code "reg,subreg,const_int")
+{
+{
+       return zip_pd_opb_operand(op);
+       return zip_pd_opb_operand(op);
+})
+})
+
+
+(define_predicate "zip_mov_operand_p"
+(define_predicate "zip_mov_operand_p"
Line 7093... Line 6942...
+(define_predicate "zip_movdst_operand_p"
+(define_predicate "zip_movdst_operand_p"
+       (match_code "mem,reg,subreg")
+       (match_code "mem,reg,subreg")
+{
+{
+       if (MEM_P(op)) // Check for valid store address
+       if (MEM_P(op)) // Check for valid store address
+               return zip_pd_opb_operand(XEXP(op,0));
+               return zip_pd_opb_operand(XEXP(op,0));
 
+       else if (SUBREG_P(op))
 
+               return 1;
 
+       else if ((REG_P(op))||(SUBREG_P(op)))
 
+               return register_operand(op, GET_MODE(op));
+       return 1;
+       return 1;
+})
+})
+
+
+(define_predicate "zip_movsrc_operand_p"
+(define_predicate "zip_movsrc_operand_p"
+       (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
+       (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
+{
+{
+       if (MEM_P(op))
+       if (MEM_P(op))
+               return zip_pd_opb_operand(XEXP(op,0));
+               return zip_pd_opb_operand(XEXP(op,0));
+       else if (GET_CODE(op)==PLUS)
+       else if (GET_CODE(op)==PLUS)
+               return zip_pd_opb_operand(op);
+               return zip_pd_opb_operand(op);
 
+       else if (SUBREG_P(op)) {
 
+               //; As far as predicates are concerned, subregs must be valid.
 
+               //; The details of them are settled within the constraints.
 
+               return 1;
 
+       } else if ((REG_P(op))||(SUBREG_P(op)))
 
+               return register_operand(op,SImode);
 
+       else if (CONST_INT_P(op))
 
+               return 1;
+       return 1;
+       return 1;
+})
+})
+
+
+;; Constraints
+;; Constraints
+;
+;
Line 7235... Line 7096...
+       }
+       }
+       //; Op[1] has a bad address, need to legitimize it
+       //; Op[1] has a bad address, need to legitimize it
+       if ((MEM_P(operands[1]))&&
+       if ((MEM_P(operands[1]))&&
+               //; (!REG_P(XEXP(operands[1],0)))
+               //; (!REG_P(XEXP(operands[1],0)))
+               ((zip_const_address_operand(XEXP(operands[1],0)))
+               ((zip_const_address_operand(XEXP(operands[1],0)))
+               ||(!zip_pd_opb_operand(XEXP(operands[1],0))))
+               ||(!zip_pd_opb_operand(XEXP(operands[1],0))))) {
+               )
 
+               {
 
+               //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
+               //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
+               if (can_create_pseudo_p()) {
+               if (can_create_pseudo_p()) {
+                       rtx tmp = gen_reg_rtx(Pmode);
+                       rtx tmp = gen_reg_rtx(Pmode);
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
+                       XEXP(operands[1],0) = tmp;
+                       XEXP(operands[1],0) = tmp;
Line 7254... Line 7113...
+       }
+       }
+       [(set_attr "ccresult" "unchanged")])
+       [(set_attr "ccresult" "unchanged")])
+(define_insn "movsi_raw"
+(define_insn "movsi_raw"
+       [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
+       [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
+               (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
+               (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
+       "(REG_P(operands[0]))||(REG_P(operands[1]))"
+       "(register_operand(operands[0],SImode))||(register_operand(operands[1],SImode))"
+       "@
+       "@
+       MOV\t%1,%0
+       MOV\t%1,%0
+       STO\t%1,%0
+       STO\t%1,%0
+       LOD\t%1,%0
+       LOD\t%1,%0
+       LDI\t%1,%0"
+       LDI\t%1,%0"
Line 7361... Line 7220...
+;
+;
+;
+;
+;
+;
+;
+;
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
 
+               ]) ])
+(define_insn "*addsi3_reg" ; Fastest/best instruction always goes first
+(define_insn "*addsi3_reg" ; Fastest/best instruction always goes first
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (plus:SI (match_operand:SI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "ADD    %2,%0"
+       "ADD    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "add<mode>3_off" ; Fastest/best instruction always goes first
+(define_insn "add<mode>3_off" ; Fastest/best instruction always goes first
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "ADD    %3+%2,%0"
+       "ADD    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
+;
+;
+(define_expand "sub<mode>3"
+(define_expand "sub<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
+       ])
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
+(define_insn "sub<mode>3_reg"
+(define_insn "sub<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "SUB    %2,%0"
+       "SUB    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "sub<mode>3_off"
+(define_insn "sub<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "SUB    %3+%2,%0"
+       "SUB    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "mul<mode>3"
+(define_insn "mul<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (mult:ZI (match_operand:ZI 1 "register_operand" "%r")
+               (mult:ZI (match_operand:ZI 1 "register_operand" "%r")
+                       (match_operand:ZI 2 "register_operand" "r")))
+                       (match_operand:ZI 2 "register_operand" "r")))
+       (clobber (match_scratch:ZI 3 "=r"))]
+       (clobber (match_scratch:ZI 3 "=r"))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
+       ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
+       ""
+       ""
+       "MOV    %1,%0
+       "MOV    %1,%0
+       MPYS    %2,%0
+       MPYS    %2,%0
+       MOV     %1,%3
+       MOV     %1,%3
Line 7429... Line 7292...
+       AND     0x0ffff,%3
+       AND     0x0ffff,%3
+       ADD     %3,%0"
+       ADD     %3,%0"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+
+
+(define_expand "div<mode>3"
+(define_expand "div<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))]
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
+       "(ZIP_DIVIDE)")
+       "(ZIP_DIVIDE)")
+(define_insn "div<mode>3_reg"
+(define_insn "div<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_DIVIDE)"
+       "(ZIP_DIVIDE)"
+       "DIVS   %2,%0"
+       "DIVS   %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "div<mode>3_off"
+(define_insn "div<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_DIVIDE)"
+       "(ZIP_DIVIDE)"
+       "DIVS   %3+%2,%0"
+       "DIVS   %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_expand "udiv<mode>3"
+(define_expand "udiv<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))]
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
+       "(ZIP_DIVIDE)")
+       "(ZIP_DIVIDE)")
+(define_insn "udiv<mode>3_reg"
+(define_insn "udiv<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_DIVIDE)"
+       "(ZIP_DIVIDE)"
+       "DIVU   %2,%0"
+       "DIVU   %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "udiv<mode>3_off"
+(define_insn "udiv<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))]
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_DIVIDE)"
+       "(ZIP_DIVIDE)"
+       "DIVU   %3+%2,%0"
+       "DIVU   %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;;
+;;
+;; modsi3
+;; modsi3
Line 7476... Line 7345...
+;;
+;;
+(define_insn "umin<mode>3"
+(define_insn "umin<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (umin:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (umin:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "register_operand" "r")))
+                       (match_operand:ZI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "CMP    %0,%2
+       "CMP    %0,%2
+       MOV.C   %2,%0"
+       MOV.C   %2,%0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "umax<mode>3"
+(define_insn "umax<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (umax:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (umax:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "register_operand" "r")))
+                       (match_operand:ZI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "CMP    %2,%0
+       "CMP    %2,%0
+       MOV.C   %2,%0"
+       MOV.C   %2,%0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "smin<mode>3"
+(define_insn "smin<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (smin:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (smin:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "register_operand" "r")))
+                       (match_operand:ZI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "CMP    %2,%0
+       "CMP    %2,%0
+       MOV.GT  %2,%0"
+       MOV.GT  %2,%0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "smax<mode>3"
+(define_insn "smax<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (smax:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (smax:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "register_operand" "r")))
+                       (match_operand:ZI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "CMP    %0,%2
+       "CMP    %0,%2
+       MOV.LT  %2,%0"
+       MOV.LT  %2,%0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_expand "and<mode>3"
+(define_expand "and<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
+(define_insn "and<mode>3_reg"
+(define_insn "and<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "rO")))]
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "AND    %2,%0"
+       "AND    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "and<mode>3_off"
+(define_insn "and<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "const_int_operand" "N"))))
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "AND    %3+%2,%0"
+       "AND    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_expand "ior<mode>3"
+(define_expand "ior<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
+(define_insn "ior<mode>3_reg"
+(define_insn "ior<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "OR     %2,%0"
+       "OR     %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "ior<mode>3_off"
+(define_insn "ior<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "nonmemory_operand" "N"))))
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "OR     %3+%2,%0"
+       "OR     %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_expand "xor<mode>3"
+(define_expand "xor<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
 
+       "")
+(define_insn "xor<mode>3_reg"
+(define_insn "xor<mode>3_reg"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rO")))
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "XOR    %2,%0"
+       "XOR    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "xor<mode>3_off"
+(define_insn "xor<mode>3_off"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+                               (match_operand:ZI 3 "nonmemory_operand" "N"))))
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "XOR    %3+%2,%0"
+       "XOR    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;(define_insn "addv<mode>4"
+;(define_insn "addv<mode>4"
+       ;[(set (match_operand:ZI 0 "register_operand" "=r")
+       ;[(set (match_operand:ZI 0 "register_operand" "=r")
+               ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
+               ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
+                       ;(match_operand:ZI 2 "general_operand" "rO")))
+                       ;(match_operand:ZI 2 "general_operand" "rO")))
+       ;(set (pc) (if_then_else (eq (cc0) (const_int 0))
+       ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
+                       ;(label_ref (match_operand 3))
+                       ;(label_ref (match_operand 3))
+                       ;(pc)))]
+                       ;(pc)))]
+       ;""
+       ;""
+       ;"MOV   %1,%0
+       ;"MOV   %1,%0
+       ;ADD    %2,%0
+       ;ADD    %2,%0
Line 7601... Line 7479...
+;;     ... ???)
+;;     ... ???)
+;;
+;;
+(define_insn "ashr<mode>3"
+(define_insn "ashr<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rR")))]
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "ASR    %2,%0"
+       "ASR    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "ashl<mode>3"
+(define_insn "ashl<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rR")))]
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "ASR    %2,%0"
+       "LSL    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "lshr<mode>3"
+(define_insn "lshr<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "register_operand" "rR")))]
+                       (match_operand:ZI 2 "register_operand" "rR")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "LSR    %2,%0"
+       "LSR    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "rotl<mode>3"
+(define_insn "rotl<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "nonmemory_operand" "rR")))]
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "ROL    %2,%0"
+       "ROL    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+(define_insn "neg<mode>2"
+(define_insn "neg<mode>2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
+               (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
+       ]
+       (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "NEG    %1,%0"
+       "NEG    %1,%0"
+       [(set_attr "ccresult" "validzn")])
+       [(set_attr "ccresult" "validzn")])
+(define_insn "abs<mode>2"
+(define_insn "abs<mode>2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
+               (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
+       ]
+       (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "TEST   %0
+       "TEST   %0
+       NEG.LT  %0"
+       NEG.LT  %0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "popcount<mode>2"
+(define_insn "popcount<mode>2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "POPC   %1,%0"
+       "POPC   %1,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_expand "parity<mode>2"
+(define_expand "parity<mode>2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
+       (set (match_dup:ZI 0) (and:ZI (match_dup:ZI 0) (const_int -2)))
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
 
+       (parallel [
 
+               (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2)))
 
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
+       ])
+       ])
+(define_insn "one_cmpl<mode>2"
+(define_insn "one_cmpl<mode>2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (not:ZI (match_operand:ZI 1 "register_operand" "0")))
+               (not:ZI (match_operand:ZI 1 "register_operand" "0")))
+       ]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       ""
+       ""
+       "XOR    -1,%0"
+       "XOR    -1,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
+;(define_extract "ssadsi"
 
+;      [(set (cc0) (compare (match_operand:SI 1 "register_operand" "+r")
 
+;                      (match_operand:SI 2 "register_operand" "+r")))
 
+;      (cond_exec (lt (cc0) (const_int 0))
 
+;         (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2))))
 
+;      (cond_exec (lt (cc0) (const_int 0))
 
+;         (set (match_dup:SI 2) (xor:SI (match_dup:SI 2) (match_dup:SI 1))))
 
+;      (cond_exec (lt (cc0) (const_int 0))
 
+;         (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2))))
 
+;      (set (match_dup:SI 2) (subtract (match_dup:SI 1) (match_dup:SI 2)))
 
+;      (set (match_operand:SI 3 "register_operand" "=r") (add:SI (match_dup:SI 2) (match_dup:SI 3)))
 
+;              ]
 
+;      "")
 
+;(define_expand "usadsi"
 
+;      [(set (cc0) (compare (match_operand:SI 1 "register_operand" "+r")
 
+;                      (match_operand:SI 2 "register_operand" "+r")))
 
+;      (cond_exec (ltu (cc0) (const_int 0))
 
+;         (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2))))
 
+;      (cond_exec (ltu (cc0) (const_int 0))
 
+;         (set (match_dup:SI 2) (xor:SI (match_dup:SI 2) (match_dup:SI 1))))
 
+;      (cond_exec (ltu (cc0) (const_int 0))
 
+;         (set (match_dup:SI 2) (xor:SI (match_dup:SI 1) (match_dup:SI 2))))
 
+;      (set (match_dup:SI 2) (subtract (match_dup:SI 1) (match_dup:SI 2)))
 
+;      (set (match_operand:SI 3 "register_operand" "=r") (add:SI (match_dup:SI 2) (match_dup:SI 3)))
 
+;              ]
 
+;      "")
 
+;
 
+;
+;
+;
+;
+;
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
Line 7706... Line 7564...
+(define_expand "movdi3"
+(define_expand "movdi3"
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
+               (match_operand:DI 1 "general_operand" ""))])
+               (match_operand:DI 1 "general_operand" ""))])
+(define_insn "movdi_lod"
+(define_insn "movdi_lod"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "r")))]
+               (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))]
+       ""
+       ""
+       {
+       {
+               if (REG_P(operands[0]))
+               if (REG_P(operands[1]))
+                       return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
+                       return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
+               else if (GET_CODE(operands[0])==PLUS) {
+               else if (GET_CODE(operands[1])==PLUS) {
+                       if ((REG_P(XEXP(operands[0],0)))
+                       if ((REG_P(XEXP(operands[1],0)))
+                               &&(CONST_INT_P(XEXP(operands[0],1)))) {
+                               &&(CONST_INT_P(XEXP(operands[1],1)))) {
+                               static  char    buf[64];
+                               static  char    buf[64];
+                               sprintf(buf,
+                               sprintf(buf,
+                                       "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
+                                       "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
+                                       INTVAL(XEXP(operands[0],1)),
+                                       INTVAL(XEXP(operands[1],1)),
+                                       INTVAL(XEXP(operands[0],1)+1));
+                                       INTVAL(XEXP(operands[1],1)+1));
+                               return buf;
+                               return buf;
+                       }
+                       }
+               } else return "BREAK";
+               } return "BREAK";
+       }
+       }
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "movdi_sto"
+(define_insn "movdi_sto"
+       [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
+       [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
+               (match_operand:DI 1 "register_operand" "r"))]
+               (match_operand:DI 1 "register_operand" "r"))]
Line 7754... Line 7612...
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "adddi3" ; Fastest/best instruction always goes first
+(define_insn "adddi3" ; Fastest/best instruction always goes first
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+(define_insn "subdi3"
+(define_insn "subdi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+(define_insn "anddi3"
+(define_insn "anddi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "AND    %L2,%L0\n\tAND\t%H2,%H0"
+       "AND    %L2,%L0\n\tAND\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+(define_insn "iordi3"
+(define_insn "iordi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "OR     %2,%0\n\tOR\t%H2,%H0"
+       "OR     %2,%0\n\tOR\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+(define_insn "xordi3"
+(define_insn "xordi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "XOR    %2,%0\n\tXOR\t%H2,%H0"
+       "XOR    %2,%0\n\tXOR\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+(define_insn "negdi2"
+(define_insn "negdi2"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))]
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
+       ""
+       ""
+       "XOR    -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
+       "XOR    -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+(define_insn "absdi2"
+(define_insn "absdi2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
+               (abs:DI (match_operand:DI 1 "register_operand" "0")))
+       (clobber (match_scratch:SI 2 "=r"))]
+       (clobber (match_scratch:SI 2 "=r"))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
+       ""
+       ""
+       "CLR    %2
+       "CLR    %2
+       TEST    %H0             ; Problem, we can't tell conditions
+       TEST    %H0             ; Problem, we can't tell conditions
+       LDILO.LT        1,%2
+       LDILO.LT        1,%2
+       XOR.LT  -1,%L0
+       XOR.LT  -1,%L0
+       XOR.LT  -1,%H0
+       XOR.LT  -1,%H0
+       ADD     %2,%L0
+       ADD     %2,%L0
+       ADD.C   %1,%HI"
+       ADD.C   1,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "one_cmpldi2"
+(define_insn "one_cmpldi2"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "XOR    -1,%L0\n\tXOR\t-1,%H0"
+       "XOR    -1,%L0\n\tXOR\t-1,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "umindi3"
+(define_insn "umindi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "CMP    %H0,%H2
+       "CMP    %H0,%H2
+       CMP.Z   %L0,%L2
+       CMP.Z   %L0,%L2
+       MOV.C   %H2,%H0
+       MOV.C   %H2,%H0
Line 7837... Line 7706...
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "umaxdi3"
+(define_insn "umaxdi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "CMP    %H2,%H0
+       "CMP    %H2,%H0
+       CMP.Z   %L2,%L0
+       CMP.Z   %L2,%L0
+       MOV.C   %H2,%H0
+       MOV.C   %H2,%H0
+       MOV.C   %L2,%L0"
+       MOV.C   %L2,%L0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "popcountdi2"
+(define_insn "popcountdi2"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (popcount (match_operand:DI 1 "register_operand" "r")))
+               (popcount:SI (match_operand:DI 1 "register_operand" "r")))
+       (clobber (match_scratch:SI 2 "=r"))
+       (clobber (match_scratch:SI 2 "=r"))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       ""
+       "POPC   %L1,%0
+       "POPC   %L1,%0
+       POPC    %H1,%2
+       POPC    %H1,%2
+       ADD     %2,%0"
+       ADD     %2,%0"
Line 7904... Line 7775...
+;
+;
+;
+;
+;
+;
+;
+;
+(define_expand "cstore<mode>4" ; Store 0 or 1 in %0 based on cmp between %2&%3
+(define_expand "cstore<mode>4" ; Store 0 or 1 in %0 based on cmp between %2&%3
+       [(set (cc0) (compare (match_operand:ZI 2 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 2 "register_operand" "r")
+               (match_operand:ZI 3 "nonmemory_operand" "rO")))
+               (match_operand:ZI 3 "zip_opb_operand_p" "rO")))
+       (set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
+       (set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
+                       (match_operator 1 "ordered_comparison_operator"
+                       (match_operator 1 "ordered_comparison_operator"
+                                       [(cc0) (const_int 0)])
+                                       [(reg:CC CC_REG) (const_int 0)])
+                       (const_int 1) (const_int 0)))]
+                       (const_int 1) (const_int 0)))]
+       ""
+       ""
+       )
+       )
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
+                       [(compare (match_operand:DI 2 "register_operand" "r")
+                       [(match_operand:DI 2 "register_operand" "r")
+                               (match_operand:DI 3 "register_operand" "r"))])
+                               (match_operand:DI 3 "register_operand" "r")])
+                       (const_int 1) (const_int 0)))]
+                       (const_int 1) (const_int 0)))
 
+       (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       {
+       {
+               switch(GET_CODE(operands[1])) {
+               switch(GET_CODE(operands[1])) {
+               case EQ:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
+               case EQ:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
+               case NE:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
+               case NE:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
Line 7946... Line 7818...
+;
+;
+;
+;
+;; This will only work so well, since the direction of the compare is
+;; This will only work so well, since the direction of the compare is
+;; important in unsigned compares.
+;; important in unsigned compares.
+;;
+;;
+(define_insn "cmp<mode>"
+(define_expand "cmp<mode>"
+       [(set (cc0) (compare (match_operand:ZI 0 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC
+               (match_operand:ZI 1 "nonmemory_operand" "rO")))]
+               (match_operand:ZI 0 "register_operand" "r")
 
+               (match_operand:ZI 1 "nonmemory_operand" "")))]
 
+       ""
 
+       {
 
+               if (!zip_opb_operand_p(operands[1],SImode)) {
 
+                       if (can_create_pseudo_p()) {
 
+                               //; fprintf(stderr, "Generating pseudo register for compare\n");
 
+                               rtx tmp = gen_reg_rtx(SImode);
 
+                               emit_insn(gen_movsi(tmp,operands[1]));
 
+                               operands[1] = tmp;
 
+                       } else FAIL;
 
+               }
 
+       })
 
+(define_insn "cmp<mode>_reg"
 
+       [(set (reg:CC CC_REG) (compare:CC
 
+               (match_operand:ZI 0 "register_operand" "r")
 
+               (match_operand:ZI 1 "zip_opb_single_operand_p" "rO")))]
+       ""
+       ""
+       "CMP\t%1,%0"
+       "CMP\t%1,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "cmp<mode>_off"
+(define_insn "cmp<mode>_off"
+       [(set (cc0) (compare (match_operand:ZI 0 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC
 
+               (match_operand:ZI 0 "register_operand" "r")
+               (plus (match_operand:ZI 1 "register_operand" "r")
+               (plus (match_operand:ZI 1 "register_operand" "r")
+                       (match_operand 2 "const_int_operand" "N"))))]
+                       (match_operand 2 "zip_opb_immv_p" "N"))))]
+       ""
+       ""
+       "CMP\t%2+%1,%0"
+       "CMP\t%2+%1,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "test<mode>"
+(define_insn "test<mode>"
+       [(set (cc0) (compare (and:ZI (match_operand:ZI 0 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_operand:ZI 0 "register_operand" "r")
+                               (match_operand:ZI 1 "nonmemory_operand" "rO"))
+                               (match_operand:ZI 1 "zip_opb_single_operand_p" "rO"))
+                       (const_int 0)))]
+                       (const_int 0)))]
+       ""
+       ""
+       "TEST   %1,%0"
+       "TEST   %1,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "test<mode>_off"
+(define_insn "test<mode>_off"
+       [(set (cc0) (compare (and:ZI (match_operand:ZI 0 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC
 
+               (and:ZI (match_operand:ZI 0 "register_operand" "r")
+                               (plus:ZI
+                               (plus:ZI
+                                 (match_operand:ZI 1 "register_operand" "r")
+                                 (match_operand:ZI 1 "register_operand" "r")
+                                 (match_operand:ZI 2 "const_int_operand" "N")))
+                               (match_operand:ZI 2 "zip_opb_immv_p" "N")))
+                       (const_int 0)))]
+                       (const_int 0)))]
+       ""
+       ""
+       "TEST   %2+%1,%0"
+       "TEST   %2+%1,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "nop"
+(define_insn "nop"
Line 7996... Line 7886...
+; other conditions then these.  That is, (cond_exec ...) is not as well
+; other conditions then these.  That is, (cond_exec ...) is not as well
+; recognized as (if_then_else ...).  So we have to duplicate things to support
+; recognized as (if_then_else ...).  So we have to duplicate things to support
+; both methods.
+; both methods.
+;
+;
+(define_cond_exec
+(define_cond_exec
+       [(ne (cc0) (const_int 0))]
+       [(ne (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
+       "(NZ)"
+       "(NZ)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+(define_cond_exec
+(define_cond_exec
+       [(lt (cc0) (const_int 0))]
+       [(lt (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
+       "(LT)"
+       "(LT)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+(define_cond_exec
+(define_cond_exec
+       [(eq (cc0) (const_int 0))]
+       [(eq (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
+       "(Z)"
+       "(Z)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+(define_cond_exec
+(define_cond_exec
+       [(gt (cc0) (const_int 0))]
+       [(gt (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
+       "(GT)"
+       "(GT)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+(define_cond_exec
+(define_cond_exec
+       [(ge (cc0) (const_int 0))]
+       [(ge (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
+       "(GE)"
+       "(GE)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+(define_cond_exec
+(define_cond_exec
+       [(ltu (cc0) (const_int 0))]
+       [(ltu (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
+       "(C)"
+       "(C)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+;
+;
+;
+;
Line 8041... Line 7931...
+; // used.
+; // used.
+;
+;
+(define_insn "set_zero_or_one<mode>"
+(define_insn "set_zero_or_one<mode>"
+       [(set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
+       [(set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
+                       (match_operator 1 "ordered_comparison_operator"
+                       (match_operator 1 "ordered_comparison_operator"
+                                       [(cc0) (const_int 0)])
+                                       [(reg:CC CC_REG) (const_int 0)])
+                       (const_int 1) (const_int 0)))]
+                       (const_int 1) (const_int 0)))]
+       ""
+       ""
+       { return (zip_set_zero_or_one(operands[1], operands[0]));
+       { return (zip_set_zero_or_one(operands[1], operands[0]));
+       }
+       }
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "mov<mode>cc"
+(define_insn "mov<mode>cc"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
+               (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
+                       [(cc0) (const_int 0)])
+                       [(reg:CC CC_REG) (const_int 0)])
+                       (match_operand:ZI 2 "general_operand" "rio")
+                       (match_operand:ZI 2 "general_operand" "rio")
+                       (match_operand:ZI 3 "nonmemory_operand" "rio")))]
+                       (match_operand:ZI 3 "nonmemory_operand" "rio")))]
+       ""
+       ""
+       {
+       {
+       return zip_movsicc(operands[0], operands[1], operands[2], operands[3]);
+       return zip_movsicc(operands[0], operands[1], operands[2], operands[3]);
+       }
+       }
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "add<mode>cc"
+(define_insn "add<mode>cc"
+       [(set (match_operand:ZI 0 "register_operand" "=r,r")
+       [(set (match_operand:ZI 0 "register_operand" "=r,r")
+               (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
+               (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
+                       [(cc0) (const_int 0)])
+                       [(reg:CC CC_REG) (const_int 0)])
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
+                               (match_operand:ZI 3 "nonmemory_operand" "rO,M"))
+                               (match_operand:ZI 3 "nonmemory_operand" "rO,M"))
+                       (match_dup 0)))]
+                       (match_dup 0)))]
+       ""
+       ""
+       {
+       {
Line 8075... Line 7965...
+;
+;
+;
+;
+;(define_expand "mov<mode>cc"
+;(define_expand "mov<mode>cc"
+;      [(set (match_operand:ZI 0 "general_operand" "=rm,rm,r,r,r"
+;      [(set (match_operand:ZI 0 "general_operand" "=rm,rm,r,r,r"
+;              (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
+;              (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
+;                      [(cc0) (const_int 0)])
+;                      [(reg:CC CC_REG) (const_int 0)])
+;                      (match_operand:ZI 2 "general_operand" "0,r,0,m,rm")
+;                      (match_operand:ZI 2 "general_operand" "0,r,0,m,rm")
+;                      (match_operand:ZI 3 "general_operand" "r,0,m,0,rm"))))]
+;                      (match_operand:ZI 3 "general_operand" "r,0,m,0,rm"))))]
+;      )
+;      )
+;
+;
+;
+;
Line 8220... Line 8110...
+;;
+;;
+;;
+;;
+;; #warning Need to adjust this so that the "LT" code doesnt get generated ...
+;; #warning Need to adjust this so that the "LT" code doesnt get generated ...
+;;
+;;
+(define_expand "cbranch<mode>4"
+(define_expand "cbranch<mode>4"
+       [(set (cc0) (compare (match_operand:ZI 1 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r")
+               (match_operand:ZI 2 "nonmemory_operand" "rO")))
+               (match_operand:ZI 2 "zip_opb_operand_p" "rO")))
+       (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
+       (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
+                       [(cc0) (const_int 0)])
+                       [(reg:CC CC_REG) (const_int 0)])
+                       (label_ref (match_operand 3 "" ""))
+                       (label_ref (match_operand 3 "" ""))
+                       (pc)))]
+                       (pc)))]
+       ""
+       ""
+       {
+       {
+               extern void zip_debug_rtx_pfx(const char *, const_rtx);
+               extern void zip_debug_rtx_pfx(const char *, const_rtx);
+               //; Two branches give us no end of difficulty when implementing.
+               //; Two branches give us no end of difficulty when implementing.
+               //; Let's check for these two branch codes, and swap the
+               //; Let's check for these two branch codes, and swap the
+               //; comparison to simplify them.
+               //; comparison to simplify them.
+               // fprintf(stderr, "CBRANCH\n");
+               //; fprintf(stderr, "CBRANCH\n");
+               // zip_debug_rtx_pfx("- CMP: ", operands[0]);
+               //; zip_debug_rtx_pfx("- CMP: ", operands[0]);
+               // zip_debug_rtx_pfx("- A  : ", operands[1]);
+               //; zip_debug_rtx_pfx("- A  : ", operands[1]);
+               // zip_debug_rtx_pfx("- B  : ", operands[2]);
+               //; zip_debug_rtx_pfx("- B  : ", operands[2]);
+               // zip_debug_rtx_pfx("- JMP: ", operands[3]);
+               //; zip_debug_rtx_pfx("- JMP: ", operands[3]);
+               //; Can we do better if we reverse some compares?
+               //; Can we do better if we reverse some compares?
+               if ((GET_CODE(operands[0])==GTU)&&(REG_P(operands[2]))) {
+               if ((GET_CODE(operands[0])==GTU)&&(REG_P(operands[2]))) {
+                       // fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n");
+                       //; fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n");
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
+                               gen_rtx_COMPARE(VOIDmode, operands[2], operands[1])));
 
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       DONE;
+                       DONE;
+               } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
+               } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
+                       // fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
+                       //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                       emit_insn(gen_cmpsi_off(operands[2], operands[1],
+                               gen_rtx_COMPARE(VOIDmode, operands[2], operands[1])));
+                                       GEN_INT(1)));
+                       emit_jump_insn(gen_cbranch_jmp_leu(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       DONE;
+                       DONE;
+               } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
+               } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
+                       // fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
+                       //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
+                       //; Swap operands, turn into a GTE compare
+                       //; Swap operands, turn into a GTE compare
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
+                               gen_rtx_COMPARE(VOIDmode, operands[2], operands[1])));
 
+                       emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
+                       DONE;
+                       DONE;
+               } // ; Otherwise ... just handle the branch normally
+               } // ; Otherwise ... just handle the branch normally
+
+
+               //; Except ... we can do better for some instructions, such as
+               //; Except ... we can do better for some instructions, such as
+               //; LE.  While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
+               //; LE.  While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
+               //; would be difficult to explain to users why MIN_INT didn't
+               //; would be difficult to explain to users why MIN_INT didn't
+               //; compare properly.  Hence we only adjust constant integers.
+               //; compare properly.  Hence we only adjust constant integers.
+               //;
+               //;
+               if ((GET_CODE(operands[0])==LE)
+               if (GET_CODE(operands[0])==LE) {
+                               &&(CONST_INT_P(operands[2]))
+                       if ((CONST_INT_P(operands[2]))
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                       // fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
+                               //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                               emit_insn(gen_cmpsi(operands[1],
+                               gen_rtx_COMPARE(VOIDmode, operands[1],
+                                               GEN_INT(INTVAL(operands[2])+1)));
+                                       GEN_INT(INTVAL(operands[2])+1))));
 
+                       emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
+                       DONE;
+                       DONE;
+               } else if ((GET_CODE(operands[0])==LEU)
+                       //; Now for the controversial ones--where we add one
+                               &&(CONST_INT_P(operands[2]))
+                       //; when it may or may not be permissable.  For now, we
 
+                       //; just do it anyway and postpone the philosophical
 
+                       //; discussion for later.
 
+                       } else if (REG_P(operands[2])) {
 
+                               emit_insn(gen_cmpsi_off(operands[1],
 
+                                               operands[2],GEN_INT(1)));
 
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
 
+                               DONE;
 
+                       } else if ((GET_CODE(operands[2])==PLUS)
 
+                               &&(REG_P(XEXP(operands[2],0)))
 
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
 
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
 
+                               emit_insn(gen_cmpsi_off(operands[1],
 
+                                               XEXP(operands[2],0),
 
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
 
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
 
+                               DONE;
 
+                       }
 
+               } else if (GET_CODE(operands[0])==LEU) {
 
+                       if ((CONST_INT_P(operands[2]))
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                       // fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
+                               //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
+                       emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+                               emit_insn(gen_cmpsi(operands[1],
+                               gen_rtx_COMPARE(VOIDmode, operands[1],
+                                               GEN_INT(INTVAL(operands[2])+1)));
+                                       GEN_INT(INTVAL(operands[2])+1))));
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
 
+                               DONE;
 
+                       //; Now for the controversial ones--this time having
 
+                       //; to do with unsigned compares.
 
+                       } else if (REG_P(operands[2])) {
 
+                               emit_insn(gen_cmpsi_off(operands[1],
 
+                                                       operands[2],GEN_INT(1)));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       DONE;
+                       DONE;
 
+                       } else if ((GET_CODE(operands[2])==PLUS)
 
+                               &&(REG_P(XEXP(operands[2],0)))
 
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
 
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
 
+                               emit_insn(gen_cmpsi_off(operands[1],
 
+                                       XEXP(operands[2],0),
 
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
 
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
 
+                               DONE;
 
+                       }
+               }
+               }
+       })
+       })
+(define_insn "cbranch_jmp_eq"
+(define_insn "cbranch_jmp_eq"
+       [(set (pc) (if_then_else (eq (cc0) (const_int 0))
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       ""
+       "BZ\t%0"
+       "BZ\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_neq"
+(define_insn "cbranch_jmp_neq"
+       [(set (pc) (if_then_else (ne (cc0) (const_int 0))
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       ""
+       "BNZ\t%0"
+       "BNZ\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_lt"
+(define_insn "cbranch_jmp_lt"
+       [(set (pc) (if_then_else (lt (cc0) (const_int 0))
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       ""
+       "BLT\t%0"
+       "BLT\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_le"
+(define_insn "cbranch_jmp_le"
+       [(set (pc) (if_then_else (le (cc0) (const_int 0))
+       [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       ""
+       "BLT\t%0
+       "BLT\t%0
+       BZ\t%0"
+       BZ\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_gt"
+(define_insn "cbranch_jmp_gt"
+       [(set (pc) (if_then_else (gt (cc0) (const_int 0))
+       [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       ""
+       "BGT\t%0"
+       "BGT\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_ge"
+(define_insn "cbranch_jmp_ge"
+       [(set (pc) (if_then_else (ge (cc0) (const_int 0))
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       ""
+       "BGE\t%0"
+       "BGE\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_ltu"
+(define_insn "cbranch_jmp_ltu"
+       [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       ""
+       "BC\t%0"
+       "BC\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_gtu"
+(define_insn "cbranch_jmp_gtu"
+       [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))
 
+       ;(clobber (reg:CC CC_REG))
 
+       ]
+       ""      ; Flip the condition, and then we can jump
+       ""      ; Flip the condition, and then we can jump
+       "XOR\t2,CC
+       "XOR\t2,CC
+       BC\t%0"
+       BC\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unknown")])
+               (set_attr "ccresult" "unknown")])
+(define_insn "cbranch_jmp_leu"
+(define_insn "cbranch_jmp_leu"
+       [(set (pc) (if_then_else (leu (cc0) (const_int 0))
+       [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""      ; Need to check for both LTU (i.e. C) and Z
+       ""      ; Need to check for both LTU (i.e. C) and Z
+       "BC\t%0
+       "BC\t%0
+       BZ\t%0"
+       BZ\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_geu"
+(define_insn "cbranch_jmp_geu"
+       [(set (pc) (if_then_else (geu (cc0) (const_int 0))
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))
 
+       ;(clobber (reg:CC CC_REG))
 
+       ]
+       ""      ; Flip the comparison, then check for GEU (once flipped)a
+       ""      ; Flip the comparison, then check for GEU (once flipped)a
+               ; Z is naturally checked for, as C would've never been set on Z
+               ; Z is naturally checked for, as C would've never been set on Z
+               ; so by flipping it, it is tantamount to saying Z or GTU.
+               ; so by flipping it, it is tantamount to saying Z or GTU.
+       "BZ\t%0
+       "BZ\t%0
+       XOR\t2,CC
+       XOR\t2,CC
Line 8385... Line 8311...
+               (set_attr "ccresult" "unknown")])
+               (set_attr "ccresult" "unknown")])
+(define_insn "cbranchdi4"
+(define_insn "cbranchdi4"
+       [(set (pc) (if_then_else
+       [(set (pc) (if_then_else
+               (match_operator 0 "ordered_comparison_operator"
+               (match_operator 0 "ordered_comparison_operator"
+                       [(match_operand:DI 1 "register_operand" "r")
+                       [(match_operand:DI 1 "register_operand" "r")
+                               (match_operand:DI 2 "nonmemory_operand" "rO")])
+                               (match_operand:DI 2 "register_operand" "r")])
+                       (label_ref (match_operand 3 "" ""))
+                       (label_ref (match_operand 3 "" ""))
+                       (pc)))
+                       (pc)))
+       (clobber (cc0))]
+       (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       {
+       {
+               switch(GET_CODE(operands[0])) {
+               switch(GET_CODE(operands[0])) {
+               case EQ:
+               case EQ:
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
Line 8456... Line 8382...
+       {
+       {
+               if (MEM_P(operands[0])) {
+               if (MEM_P(operands[0])) {
+                       // This should always be the case
+                       // This should always be the case
+                       rtx addr = XEXP(operands[0],0);
+                       rtx addr = XEXP(operands[0],0);
+                       if (zip_const_address_operand_p(addr, SImode)) {
+                       if (zip_const_address_operand_p(addr, SImode)) {
+                               // fprintf(stderr, "Generating gen_void_call_const()\n");
+                               //; fprintf(stderr, "Generating gen_void_call_const()\n");
+                               emit_call_insn(gen_void_call_const(addr,
+                               emit_call_insn(gen_void_call_const(addr,
+                                               operands[1]));
+                                               operands[1]));
+                       } else if ((MEM_P(addr))&&(zip_address_operand(
+                       } else if ((MEM_P(addr))&&(zip_address_operand(
+                                                       XEXP(addr,0)))) {
+                                                       XEXP(addr,0)))) {
+                               emit_call_insn(gen_void_call_mem(XEXP(addr,0),
+                               emit_call_insn(gen_void_call_mem(XEXP(addr,0),
Line 8489... Line 8415...
+; label gets removed and the call gets lost.  Hence we do it this way (below).
+; label gets removed and the call gets lost.  Hence we do it this way (below).
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
+; recognize as such, but for now we'll use .Lcall# as our label.
+; recognize as such, but for now we'll use .Lcall# as our label.
+;
+;
+(define_insn "void_call_const"
+(define_insn "void_call_const"
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+       [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+                       (match_operand 1 "const_int_operand" "n"))
+                       (match_operand 1 "const_int_operand" "n"))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))
 
+               (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "void_call_mem"
+(define_insn "void_call_mem"
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+       [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+                       (match_operand 1 "const_int_operand" "n"))
+                       (match_operand 1 "const_int_operand" "n"))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))
 
+               (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+(define_insn "void_call_var"
+(define_insn "void_call_var"
+       [(parallel [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+       [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+                       (match_operand 1 "const_int_operand" "n"))
+                       (match_operand 1 "const_int_operand" "n"))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))
 
+               (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_expand "call_value"
+(define_expand "call_value"
+       [(set (reg:SI RTNV_REG)
+       [(parallel [(set (reg:SI RTNV_REG)
+               (call (match_operand:SI 1 "" "")
+               (call (match_operand:SI 1 "" "")
+                       (match_operand 2 "const_int_operand" "n")))
+                       (match_operand 2 "const_int_operand" "n")))
+       (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))]
+       (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))
 
+       (clobber (reg:CC CC_REG))])]
+       ""
+       ""
+       {
+       {
+               // extern void zip_debug_rtx(const_rtx);
+               //; extern void zip_debug_rtx(const_rtx);
+               // fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
+               //; fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
+               // zip_debug_rtx(operands[1]);
+               //; zip_debug_rtx(operands[1]);
+               if (MEM_P(operands[1])) {
+               if (MEM_P(operands[1])) {
+                       // fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n");
+                       //; fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n");
+                       // zip_debug_rtx(operands[1]);
+                       //; zip_debug_rtx(operands[1]);
+                       // This should always be the case
+                       //; This should always be the case
+                       rtx addr = XEXP(operands[1],0);
+                       rtx addr = XEXP(operands[1],0);
+                       if (zip_const_address_operand_p(addr, SImode)) {
+                       if (zip_const_address_operand_p(addr, SImode)) {
+                               // fprintf(stderr, "Generating gen_reg_call_const()\n");
+                               //; fprintf(stderr, "Generating gen_reg_call_const()\n");
+                               emit_call_insn(gen_reg_call_const(addr, operands[2]));
+                               emit_call_insn(gen_reg_call_const(addr, operands[2]));
+                       } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
+                       } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
+                               // fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
+                               emit_call_insn(gen_reg_call_mem(XEXP(addr,0), operands[2]));
+                               emit_call_insn(gen_reg_call_mem(XEXP(addr,0), operands[2]));
+                       } else {
+                       } else {
+                               // fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
+                               emit_call_insn(gen_reg_call_var(addr, operands[2]));
+                               emit_call_insn(gen_reg_call_var(addr, operands[2]));
+                       }
+                       }
+                       DONE;
+                       DONE;
+               }
+               }
+       })
+       })
+(define_insn "reg_call_const"
+(define_insn "reg_call_const"
+       [(parallel [(set (reg:SI RTNV_REG)
+       [(set (reg:SI RTNV_REG)
+               (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+               (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+                       (match_operand 1 "const_int_operand" "n")))
+                       (match_operand 1 "const_int_operand" "n")))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))
 
+               (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "reg_call_mem"
+(define_insn "reg_call_mem"
+       [(set (reg:SI RTNV_REG)
+       [(set (reg:SI RTNV_REG)
+               (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+               (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+                       (match_operand 1 "const_int_operand" "n")))
+                       (match_operand 1 "const_int_operand" "n")))
+               (clobber (reg:SI RTN_REG))]
+               (clobber (reg:SI RTN_REG))
 
+               (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+(define_insn "reg_call_var"
+(define_insn "reg_call_var"
+       [(parallel [(set (reg:SI RTNV_REG)
+       [(set (reg:SI RTNV_REG)
+               (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+               (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+                       (match_operand 1 "const_int_operand" "n")))
+                       (match_operand 1 "const_int_operand" "n")))
+               (clobber (reg:SI RTN_REG))])]
+               (clobber (reg:SI RTN_REG))
 
+               (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "MOV    .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
+       "MOV    .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+;
+;
Line 8612... Line 8545...
+;
+;
+;
+;
+;
+;
+(define_insn "zip_rtu"
+(define_insn "zip_rtu"
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_RTU)
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_RTU)
+       (clobber (cc0))]
+       (clobber (reg:CC CC_REG))]
+       "(!ZIP_USER)"
+       "(!ZIP_USER)"
+       "RTU"
+       "RTU"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+(define_insn "zip_halt" ; Needs to be unspec_volatile, or optimizer will opt out
+(define_insn "zip_halt" ; Needs to be unspec_volatile, or optimizer will opt out
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_HALT)
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_HALT)
+       (clobber (cc0))]
+       (clobber (reg:CC CC_REG))]
+       "(!ZIP_USER)"
+       "(!ZIP_USER)"
+       "HALT"
+       "HALT"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+(define_insn "zip_idle"
+(define_insn "zip_idle"
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_IDLE)
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_IDLE)
+       (clobber (cc0))]
+       (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "WAIT"
+       "WAIT"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+(define_insn "zip_syscall"
+(define_insn "zip_syscall"
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_SYSCALL)]
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_SYSCALL)]
Line 8683... Line 8616...
+       MOV\tuPC,%4
+       MOV\tuPC,%4
+       STO\t%1,12(%0)
+       STO\t%1,12(%0)
+       STO\t%2,13(%0)
+       STO\t%2,13(%0)
+       STO\t%3,14(%0)
+       STO\t%3,14(%0)
+       STO\t%4,15(%0)"
+       STO\t%4,15(%0)"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+;
+;
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
+; even though we don't really read (or change) its value throughout this
+; even though we don't really read (or change) its value throughout this
+; operation.
+; operation.
+;
+;
Line 8729... Line 8662...
+       LOD\t15(%0),%4
+       LOD\t15(%0),%4
+       MOV\t%1,uR12
+       MOV\t%1,uR12
+       MOV\t%2,uSP
+       MOV\t%2,uSP
+       MOV\t%3,uCC
+       MOV\t%3,uCC
+       MOV\t%4,uPC"
+       MOV\t%4,uPC"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "zip_bitrev"
+(define_insn "zip_bitrev"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_BITREV))
+               (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_BITREV))
+       ]
+       ]
+       ""
+       ""
+       "BREV\t%1,%0"
+       "BREV\t%1,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "unchanged")])
+(define_insn "zip_cc"
+(define_insn "zip_cc"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
+       ""
+       ""
+       "MOV\tCC,%0"
+       "MOV\tCC,%0"
Line 8784... Line 8717...
+;
+;
+;
+;
+(define_insn "addsf3"
+(define_insn "addsf3"
+       [(set (match_operand:SF 0 "register_operand" "=r")
+       [(set (match_operand:SF 0 "register_operand" "=r")
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
+                       (match_operand:SF 2 "register_operand" "r")))]
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_FPU)"
+       "(ZIP_FPU)"
+       "FPADD  %2,%0"
+       "FPADD  %2,%0"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+(define_insn "subsf3"
+(define_insn "subsf3"
+       [(set (match_operand:SF 0 "register_operand" "=r")
+       [(set (match_operand:SF 0 "register_operand" "=r")
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
+                       (match_operand:SF 2 "register_operand" "r")))]
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_FPU)"
+       "(ZIP_FPU)"
+       "FPSUB  %2,%0"
+       "FPSUB  %2,%0"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+(define_insn "mulsf3"
+(define_insn "mulsf3"
+       [(set (match_operand:SF 0 "register_operand" "=r")
+       [(set (match_operand:SF 0 "register_operand" "=r")
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
+                       (match_operand:SF 2 "register_operand" "r")))]
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_FPU)"
+       "(ZIP_FPU)"
+       "FPMUL  %2,%0"
+       "FPMUL  %2,%0"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+(define_insn "divsf3"
+(define_insn "divsf3"
+       [(set (match_operand:SF 0 "register_operand" "=r")
+       [(set (match_operand:SF 0 "register_operand" "=r")
+               (div:SF (match_operand:SF 1 "register_operand" "0")
+               (div:SF (match_operand:SF 1 "register_operand" "0")
+                       (match_operand:SF 2 "register_operand" "r")))]
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_FPU)"
+       "(ZIP_FPU)"
+       "FPDIV  %2,%0"
+       "FPDIV  %2,%0"
+       [(set_attr "ccresult" "unknown")])
+       [(set_attr "ccresult" "unknown")])
+(define_expand "negsf2"
+(define_expand "negsf2"
+       [(set (match_operand:SF 0 "register_operand" "=r")
+       [(set (match_operand:SF 0 "register_operand" "=r")
Line 8819... Line 8756...
+       {
+       {
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+               if (can_create_pseudo_p()) {
+               if (can_create_pseudo_p()) {
+                       rtx tmp = gen_reg_rtx(SImode);
+                       rtx tmp = gen_reg_rtx(SImode);
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
+                       emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_XOR(SImode, operands[0], tmp)));
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
+                       DONE;
+                       DONE;
+               } else {
+               } else {
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_IOR(SImode, operands[0],gen_int_mode(1,SImode))));
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
 
+                               gen_int_mode(1,SImode)));
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       DONE;
+                       DONE;
+               }
+               }
+       })
+       })
+(define_expand "abssf2"
+(define_expand "abssf2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:SF 0 "register_operand" "=r")
+               (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
+       ]
+       ]
+       ""
+       ""
+       {
+       {
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+               if (can_create_pseudo_p()) {
+               if (can_create_pseudo_p()) {
+                       rtx tmp = gen_reg_rtx(SImode);
+                       rtx tmp = gen_reg_rtx(SImode);
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
+                       emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_AND(SImode, operands[0], tmp)));
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
+                       DONE;
+                       DONE;
+               } else {
+               } else {
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       emit_insn(gen_rtx_SET(SImode, operands[0],
+                       emit_insn(gen_andsi3(operands[0], operands[0],
+                               gen_rtx_AND(SImode, operands[0],
+                               gen_int_mode(-2,SImode)));
+                               gen_int_mode(-2,SImode))));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       DONE;
+                       DONE;
+               }
+               }
+       })
+       })
+;
+;
Line 8874... Line 8811...
+       ""
+       ""
+       "BREAK"
+       "BREAK"
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+;
+;
+(define_expand "ctrap<mode>4"
+(define_expand "ctrap<mode>4"
+       [(set (cc0) (compare (match_operand:ZI 1 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC
+               (match_operand:ZI 2 "nonmemory_operand" "rO")))
+               (match_operand:ZI 1 "register_operand" "r")
 
+               (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+       (trap_if (match_operator 0 "ordered_comparison_operator"
+       (trap_if (match_operator 0 "ordered_comparison_operator"
+                       [(cc0) (const_int 0)])
+                       [(reg:CC CC_REG) (const_int 0)])
+                       (match_operand 3 "const_int_operand" "O"))]
+                       (match_operand 3 "const_int_operand" "O"))]
+       ""
+       ""
+       )
+       )
+(define_insn "trapif"
+(define_insn "trapif"
+       [(trap_if (match_operator 0 "ordered_comparison_operator"
+       [(trap_if (match_operator 0 "ordered_comparison_operator"
+                       [(cc0) (const_int 0)])
+                       [(reg:CC CC_REG) (const_int 0)])
+                       (match_operand 1 "const_int_operand" "O"))]
+                       (match_operand 1 "const_int_operand" "O"))]
+       ""
+       ""
+       "BREAK\t%1"
+       "BREAK\t%1"
+       [(set_attr "predicable" "no")])
+       [(set_attr "predicable" "no")])
+;
+;
Line 8899... Line 8837...
+;;
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+;
+;
+;
+;
+;
+; The book says that add<mode>3 is used if addptr<mode>3 is undefined.
 
+; Hence we leave this as unimplemented.
 
+;
 
+;(define_insn "addptrsi3"
 
+;      [(set (match_operand:SI 0 "register_operand" "=r")
 
+;              (plus:SI (match_operand:SI 1 "register_operand" "r")
 
+;                      (match_operand:SI 2 "general_operand" "M")))]
 
+;      ; Addptr is not allowed to clobber condition codes, thus we *must*
 
+;      ; use the mov (A+B),C form of the add.
 
+;      ""
 
+;      "MOV    %2(%1),%0"
 
+;      [(set_attr "ccresult" "unchanged")])
 
+;
 
+; (define_insn "casesi"
 
+;      "LDI    %4,R0
 
+;      SUB     %2,%1
 
+;      BLT     %5
 
+;      CMP     %3,%1
 
+;      BGT     %5
 
+;      ADD     %1,R0
 
+;      LOD     (R0),pc"
 
+;      "")
 
+; (define_insn "decrement_and_branch_until_zero"
 
+       ; [(parallel [
 
+               ; (set (match_operand:SI 0 "regiser_operand" "r")
 
+                       ; (minus:SI (match_dup 0) (const_int 1)))
 
+               ; (set (pc) (if_then_else
 
+                               ; (ge (minus:SI (match_dup 0) (const_int 1)))
 
+                               ; (label_ref (match_operand 1 "" ""))
 
+                               ; (pc)))])]
 
+       ; ""
 
+; ;    SUB     1,%0
 
+; ;    BNZ     %1
 
+; ;     .vice the faster (optimize for speed)
 
+       ; "SUB  1,%0
 
+       ; BZ    %=
 
+       ; BRA   %1
 
+       ; %=:"
 
+       ; [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
 
+; doloop_end - do not define--would require cost of an unopt register to use
 
+; allocate_stack       - do not define ...
 
+; nonlocal_goto - do not define
 
+;(define_insn "ctrapmm4"
 
+;      CMP     %1,%2
 
+;      MOV.%0  %3,R0
 
+;      LDILO.%0 0,(CC)
 
+;
 
+;(define_insn "sync_compare_and_swapsi"
+;(define_insn "sync_compare_and_swapsi"
+;      [(set ...
+;      [(set ...
+;              )]
+;              )]
+;      "(ZIP_ATMOC)"
+;      "(ZIP_ATMOC)"
+;      LOCK            (alu)           // Hmmm ... need to modify if I will
+;      LOCK            (alu)           // Hmmm ... need to modify if I will
Line 8972... Line 8863...
+;      ADD     1,%0
+;      ADD     1,%0
+;      BV      %2"
+;      BV      %2"
+;      "")
+;      "")
+
+
+(define_peephole2
+(define_peephole2
+       [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+       [(set (reg:CC CC_REG) (compare:CC
+               (match_operand:SI 1 "register_operand" "")))
+               (match_operand:SI 0 "register_operand")
+       (set (pc) (if_then_else (gtu (cc0) (const_int 0))
+               (match_operand:SI 1 "register_operand")))
+                       (label_ref (match_operand 2 "" ""))
+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
 
+                       (label_ref (match_operand 2 ""))
+                       (pc)))]
+                       (pc)))]
+       ""
+       ""
+       [(set (cc0) (compare (match_dup 1) (match_dup 0)))
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))
+       (set (pc) (if_then_else (ltu (cc0) (const_int 0))
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
+                       (label_ref (match_dup 2))
+                       (label_ref (match_dup 2))
+                       (pc)))]
+                       (pc)))]
+       "")
+       "")
+(define_peephole2
+(define_peephole2
+       [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+       [(set (reg:CC CC_REG) (compare:CC
+               (match_operand:SI 1 "register_operand" "")))
+               (match_operand:SI 0 "register_operand")
+       (set (pc) (if_then_else (geu (cc0) (const_int 0))
+               (match_operand:SI 1 "register_operand")))
+                       (label_ref (match_operand 2 "" ""))
+       (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
 
+                       (label_ref (match_operand 2 ""))
+                       (pc)))]
+                       (pc)))]
+       ""
+       ""
+       [(set (cc0) (compare (match_dup 1) (plus (match_dup 0) (const_int 1))))
+       [(set (reg:CC CC_REG) (compare:CC
+       (set (pc) (if_then_else (ltu (cc0) (const_int 0))
+               (match_dup 1) (plus (match_dup 0) (const_int 1))))
 
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
+                       (label_ref (match_dup 2))
+                       (label_ref (match_dup 2))
+                       (pc)))]
+                       (pc)))]
+       "")
+       "")
+(define_peephole2
+(define_peephole2
+       [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+       [(set (reg:CC CC_REG) (compare:CC
+               (match_operand:SI 1 "register_operand" "")))
+               (match_operand:SI 0 "register_operand")
+       (set (pc) (if_then_else (ge (cc0) (const_int 0))
+               (match_operand:SI 1 "register_operand")))
+                       (label_ref (match_operand 2 "" ""))
+       (set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
 
+                       (label_ref (match_operand 2 ""))
+                       (pc)))]
+                       (pc)))]
+       ""
+       ""
+       [(set (cc0) (compare (match_dup 1) (match_dup 0)))
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1)
+       (set (pc) (if_then_else (le (cc0) (const_int 0))
+                       (plus:SI (match_dup 0) (const_int 1))))
 
+       (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
+                       (label_ref (match_dup 2))
+                       (label_ref (match_dup 2))
+                       (pc)))]
+                       (pc)))]
+       "")
+       "")
+(define_peephole2
+(define_peephole2
+       [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+       [(set (reg:CC CC_REG) (compare:CC
 
+               (match_operand:SI 0 "register_operand" "")
+               (match_operand:SI 1 "register_operand" "")))
+               (match_operand:SI 1 "register_operand" "")))
+       (set (pc) (if_then_else (leu (cc0) (const_int 0))
+       (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
+                       (label_ref (match_operand 2 "" ""))
+                       (label_ref (match_operand 2 "" ""))
+                       (pc)))]
+                       (pc)))]
+       ""
+       ""
+       [(set (cc0) (compare (match_dup 0) (plus (match_dup 1) (const_int 1))))
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
+       (set (pc) (if_then_else (ltu (cc0) (const_int 0))
+                       (plus (match_dup 1) (const_int 1))))
 
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
+                       (label_ref (match_dup 2))
+                       (label_ref (match_dup 2))
+                       (pc)))]
+                       (pc)))]
+       "")
+       "")
+;
+;
+; I need to revisit these peephole optimizations when I can come up with another
+; I need to revisit these peephole optimizations when I can come up with another
+; way of adding one to the constant integer.  The approach listed below just
+; way of adding one to the constant integer.  The approach listed below just
+; ... doesn't work.
+; ... doesn't work.
+;
+;
+;(define_peephole2
+;(define_peephole2
+;      [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+;      [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "")
+;              (match_operand:SI 1 "const_int_operand" "")))
+;              (match_operand:SI 1 "const_int_operand" "")))
+;      (set (pc) (if_then_else (le (cc0) (const_int 0))
+;      (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
+;                      (label_ref (match_operand 2 "" ""))
+;                      (label_ref (match_operand 2 "" ""))
+;                      (pc)))]
+;                      (pc)))]
+;      "(INTVAL(operands[1])<((1<<17)-2))"
+;      "(INTVAL(operands[1])<((1<<17)-2))"
+;      [(set (cc0) (compare (match_dup 0) (plus (match_dup 1) (const_int 1))))
+;      [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1))))
+;      (set (pc) (if_then_else (lt (cc0) (const_int 0))
+;      (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
+;                      (label_ref (match_dup 2))
+;                      (label_ref (match_dup 2))
+;                      (pc)))]
+;                      (pc)))]
+;      "")
+;      "")
+;(define_peephole2
+;(define_peephole2
+;      [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+;      [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "")
+;              (match_operand:SI 1 "const_int_operand" "")))
+;              (match_operand:SI 1 "const_int_operand" "")))
+;      (set (pc) (if_then_else (leu (cc0) (const_int 0))
+;      (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
+;                      (label_ref (match_operand 2 "" ""))
+;                      (label_ref (match_operand 2 "" ""))
+;                      (pc)))]
+;                      (pc)))]
+;      "(INTVAL(operands[1])<((1<<17)-2))"
+;      "(INTVAL(operands[1])<((1<<17)-2))"
+;      [(set (cc0) (compare (match_dup 0) (plus (match_dup 1) (const_int 1))))
+;      [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1))))
+;      (set (pc) (if_then_else (lt (cc0) (const_int 0))
+;      (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
+;                      (label_ref (match_dup 2))
+;                      (label_ref (match_dup 2))
+;                      (pc)))]
+;                      (pc)))]
+;      "")
+;      "")
+;
+;
+;
+;
Line 9058... Line 8956...
+;      (set (pc) (label))]
+;      (set (pc) (label))]
+;      To result with
+;      To result with
+;      "MOV\tlabel,R0
+;      "MOV\tlabel,R0
+;      JMP\tsubroutine"
+;      JMP\tsubroutine"
+;
+;
 
+; and for
 
+;      BRA target
 
+;      BRA target ; two branches to the same identical target in a row ...
 
+;
 
+;
 
+;
 
+; Match:
 
+;      MOV A(R1),R3
 
+;      CMP R3,R0
 
+;      (R3 is dead)
 
+; Transform to:
 
+;      CMP A(R1),R0
 
+;
 
+(define_peephole2
 
+       [(set (match_operand:SI 3 "register_operand")
 
+               (plus:SI (match_operand:SI 1 "register_operand")
 
+                       (match_operand:SI 2 "zip_mvimm_operand_p")))
 
+       (set (reg:CC CC_REG)
 
+               (compare:CC (match_operand:SI 0 "register_operand")
 
+                       (match_dup 3)))]
 
+       "peep2_regno_dead_p(2, REGNO(operands[3]))"
 
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
 
+               (plus:SI (match_dup 1) (match_dup 2))))]
 
+       "")
 
+;
 
+;
 
+; Match:
 
+;      ALU OpB,R0
 
+;      CMP 0,R0
 
+; Transform to:
 
+;      ALU OpB,R0
 
+;
 
+(define_peephole2
 
+       [(parallel [(set (match_operand 0 "register_operand")
 
+                       (match_operand 1 ""))
 
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       ""
 
+       [(parallel [(set (match_dup 0) (match_dup 1))
 
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
 
+       ])
 
+;
 
+;
 
+; Match:
 
+;      ALU OpB,R0
 
+;      MOV R1,R2       // Can be LDI, LOD, STO, etc.
 
+;      CMP 0,R1
 
+; Transform to:
 
+;      ALU OpB,R0
 
+;      MOV R0,R1
 
+;
 
+(define_peephole2
 
+       [(parallel [(set (match_operand 0 "register_operand")
 
+                       (match_operand 1 ""))
 
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
 
+       (set (match_operand 2 "nonimmediate_operand") (match_operand 3 ""))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG)))"
 
+       [(parallel [(set (match_dup 0) (match_dup 1))
 
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
 
+       (set (match_dup 2) (match_dup 3))
 
+       ])
 
+;
 
+;
 
+; Match:
 
+;      ALU OpB,R0
 
+;      MOV R0,R1
 
+;      CMP 0,R1
 
+; Transform to:
 
+;      ALU OpB,R0
 
+;      MOV R0,R1
 
+;
 
+(define_peephole2
 
+       [(parallel [(set (match_operand 0 "register_operand")
 
+                       (match_operand 1 ""))
 
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
 
+       (set (match_operand 2 "register_operand") (match_dup 0))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]
 
+       ""
 
+       [(parallel [(set (match_dup 0) (match_dup 1))
 
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
 
+       (set (match_dup 2) (match_dup 3))
 
+       ])
 
+
 
+;
+; STILL MISSING:
+; STILL MISSING:
+;      SYSCALL(ID)
+;      SYSCALL(ID)
+;              MOV %ID,R0
+;              MOV %ID,R0
+;              CLR     CC
+;              CLR     CC
+;      cmove   ... the conditional move, created from a
+;      cmove   ... the conditional move, created from a
Line 9094... Line 9077...
+// change needed to be made in machmodes.def.  Hence, here is a target
+// change needed to be made in machmodes.def.  Hence, here is a target
+// configuration change--in machmodes.def--that properly belonged in the
+// configuration change--in machmodes.def--that properly belonged in the
+// config directory.
+// config directory.
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-03-12 17:39:02.331344108 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-04-06 14:25:35.431154171 -0400
@@ -0,0 +1,70 @@
@@ -0,0 +1,78 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   zip-protos.h
+// Filename:   zip-protos.h
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 9144... Line 9127...
+extern enum    reg_class       zip_reg_class(int);
+extern enum    reg_class       zip_reg_class(int);
+extern rtx     zip_return_addr_rtx(int, rtx);
+extern rtx     zip_return_addr_rtx(int, rtx);
+extern int     zip_num_arg_regs(enum machine_mode, tree);
+extern int     zip_num_arg_regs(enum machine_mode, tree);
+
+
+extern void    zip_asm_output_def(FILE *s, const char *n, const char *v);
+extern void    zip_asm_output_def(FILE *s, const char *n, const char *v);
 
+
 
+#ifdef HAVE_cc0
+extern void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
+extern void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
 
+#else
 
+extern void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
 
+#endif
+extern int     zip_address_operand(rtx op);
+extern int     zip_address_operand(rtx op);
+extern int     zip_const_address_operand(rtx op);
+extern int     zip_const_address_operand(rtx op);
+extern bool    zip_gen_move_rtl(rtx, rtx);
+extern bool    zip_gen_move_rtl(rtx, rtx);
+// extern      bool    zip_load_address_lod(rtx, rtx);
 
+// extern      bool    zip_load_address_sto(rtx, rtx);
 
+extern bool    zip_use_return_insn(void);
+extern bool    zip_use_return_insn(void);
+extern const char *zip_set_zero_or_one(rtx, rtx);
+extern const char *zip_set_zero_or_one(rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+
+
+extern int     zip_ct_address_operand(rtx op);
+extern int     zip_ct_address_operand(rtx op);
Line 9164... Line 9150...
+extern int     zip_ct_const_address_operand(rtx op);
+extern int     zip_ct_const_address_operand(rtx op);
+extern int     zip_pd_const_address_operand(rtx op);
+extern int     zip_pd_const_address_operand(rtx op);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
+
+
 
+extern void    zip_ifcvt_machdep_init(struct ce_if_block *ceinfo);
 
+extern void    zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo);
 
+extern void    zip_ifcvt_modify_final(struct ce_if_block *ceinfo);
 
+extern void    zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
 
+
+#endif
+#endif
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config.gcc        2016-02-14 00:53:37.389411987 -0500
+++ gcc-5.3.0-zip/gcc/config.gcc        2016-02-14 00:53:37.389411987 -0500
Line 9198... Line 9189...
 *)
 *)
        echo "*** Configuration ${target} not supported" 1>&2
        echo "*** Configuration ${target} not supported" 1>&2
        exit 1
        exit 1
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
--- gcc-5.3.0-original/gcc/cse.c        2015-02-03 15:41:38.000000000 -0500
--- gcc-5.3.0-original/gcc/cse.c        2015-02-03 15:41:38.000000000 -0500
+++ gcc-5.3.0-zip/gcc/cse.c     2016-03-19 12:28:45.584701098 -0400
+++ gcc-5.3.0-zip/gcc/cse.c     2016-04-05 22:26:30.816200542 -0400
@@ -634,6 +634,15 @@
@@ -634,6 +634,15 @@
 
 
 /* Nonzero if X has the form (PLUS frame-pointer integer).  */
 /* Nonzero if X has the form (PLUS frame-pointer integer).  */
 
 
+// #define     DO_ZIP_DEBUGS
+// #define     DO_ZIP_DEBUGS
Line 9597... Line 9588...
 rtx
 rtx
 expand_expr_real (tree exp, rtx target, machine_mode tmode,
 expand_expr_real (tree exp, rtx target, machine_mode tmode,
                  enum expand_modifier modifier, rtx *alt_rtl,
                  enum expand_modifier modifier, rtx *alt_rtl,
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
--- gcc-5.3.0-original/gcc/final.c      2015-01-15 08:28:42.000000000 -0500
--- gcc-5.3.0-original/gcc/final.c      2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/final.c   2016-03-29 08:41:03.919647461 -0400
+++ gcc-5.3.0-zip/gcc/final.c   2016-04-06 10:11:34.628479923 -0400
@@ -109,6 +109,14 @@
@@ -109,6 +109,14 @@
 #include "wide-int-print.h"
 #include "wide-int-print.h"
 #include "rtl-iter.h"
 #include "rtl-iter.h"
 
 
+
+// #define     DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+extern void zip_debug_rtx(const_rtx);
+extern void zip_debug_rtx(const_rtx);
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
+#else
+#else
+#define        ZIP_DEBUG_LINE(STR,RTX)
+#define        ZIP_DEBUG_LINE(STR,RTX)
Line 9706... Line 9697...
 
 
   print_closer ();
   print_closer ();
 }
 }
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/jump.c gcc-5.3.0-zip/gcc/jump.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/jump.c gcc-5.3.0-zip/gcc/jump.c
--- gcc-5.3.0-original/gcc/jump.c       2015-01-27 04:19:30.000000000 -0500
--- gcc-5.3.0-original/gcc/jump.c       2015-01-27 04:19:30.000000000 -0500
+++ gcc-5.3.0-zip/gcc/jump.c    2016-04-01 06:41:10.724002408 -0400
+++ gcc-5.3.0-zip/gcc/jump.c    2016-04-06 14:06:50.207563805 -0400
@@ -80,6 +80,14 @@
@@ -80,6 +80,14 @@
 #include "target.h"
 #include "target.h"
 #include "rtl-iter.h"
 #include "rtl-iter.h"
 
 
+// #define     DO_ZIP_DEBUGS
+// #define     DO_ZIP_DEBUGS
Line 9983... Line 9974...
   return apply_change_group ();
   return apply_change_group ();
 }
 }
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
--- gcc-5.3.0-original/gcc/recog.c      2015-03-20 02:07:30.000000000 -0400
--- gcc-5.3.0-original/gcc/recog.c      2015-03-20 02:07:30.000000000 -0400
+++ gcc-5.3.0-zip/gcc/recog.c   2016-03-29 08:44:33.142234843 -0400
+++ gcc-5.3.0-zip/gcc/recog.c   2016-04-06 17:45:29.552304498 -0400
@@ -68,6 +68,15 @@
@@ -68,6 +68,15 @@
 #include "df.h"
 #include "df.h"
 #include "insn-codes.h"
 #include "insn-codes.h"
 
 
+// #define     DO_ZIP_DEBUGS
+// #define     DO_ZIP_DEBUGS
Line 10000... Line 9991...
+
+
+
+
 #ifndef STACK_PUSH_CODE
 #ifndef STACK_PUSH_CODE
 #ifdef STACK_GROWS_DOWNWARD
 #ifdef STACK_GROWS_DOWNWARD
 #define STACK_PUSH_CODE PRE_DEC
 #define STACK_PUSH_CODE PRE_DEC
@@ -3671,7 +3680,6 @@
@@ -2283,6 +2292,7 @@
 
   recog_data.n_dups = 0;
 
   recog_data.is_asm = false;
 
 
 
+ZIP_DEBUG_LINE("Extract-insn", insn);
 
   switch (GET_CODE (body))
 
     {
 
     case USE:
 
@@ -3671,7 +3681,6 @@
            break;
            break;
 
 
          /* The buffer filled to the current maximum, so try to match.  */
          /* The buffer filled to the current maximum, so try to match.  */
-
-
          pos = peep2_buf_position (peep2_current + peep2_current_count);
          pos = peep2_buf_position (peep2_current + peep2_current_count);
          peep2_insn_data[pos].insn = PEEP2_EOB;
          peep2_insn_data[pos].insn = PEEP2_EOB;
          COPY_REG_SET (peep2_insn_data[pos].live_before, live);
          COPY_REG_SET (peep2_insn_data[pos].live_before, live);
@@ -3704,6 +3712,7 @@
@@ -3704,6 +3713,7 @@
     rebuild_jump_labels (get_insns ());
     rebuild_jump_labels (get_insns ());
   if (peep2_do_cleanup_cfg)
   if (peep2_do_cleanup_cfg)
     cleanup_cfg (CLEANUP_CFG_CHANGED);
     cleanup_cfg (CLEANUP_CFG_CHANGED);
+
+
 }
 }
 #endif /* HAVE_peephole2 */
 #endif /* HAVE_peephole2 */
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
--- gcc-5.3.0-original/gcc/reload1.c    2015-01-15 08:28:42.000000000 -0500
--- gcc-5.3.0-original/gcc/reload1.c    2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-01 06:34:13.138506735 -0400
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-06 17:44:36.240674020 -0400
@@ -72,6 +72,14 @@
@@ -72,6 +72,14 @@
 #include "dumpfile.h"
 #include "dumpfile.h"
 #include "rtl-iter.h"
 #include "rtl-iter.h"
 
 
+// #define     DO_ZIP_DEBUGS
+// #define     DO_ZIP_DEBUGS
Line 10074... Line 10073...
   return need_dce;
   return need_dce;
 }
 }
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
--- gcc-5.3.0-original/gcc/reload.c     2015-01-15 08:28:42.000000000 -0500
--- gcc-5.3.0-original/gcc/reload.c     2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/reload.c  2016-03-19 12:28:30.592811127 -0400
+++ gcc-5.3.0-zip/gcc/reload.c  2016-04-06 17:49:33.418613170 -0400
@@ -2707,8 +2707,17 @@
@@ -136,6 +136,15 @@
 
 #include "target.h"
 
 #include "ira.h"
 
 
 
+// #define     DO_ZIP_DEBUGS
 
+#ifdef DO_ZIP_DEBUGS
 
+extern void zip_debug_rtx(const_rtx);
 
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
 
+#else
 
+#define        ZIP_DEBUG_LINE(STR,RTX)
 
+#endif
 
+
 
+
 
 /* True if X is a constant that can be forced into the constant pool.
 
    MODE is the mode of the operand, or VOIDmode if not known.  */
 
 #define CONST_POOL_OK_P(MODE, X)               \
 
@@ -2700,6 +2709,8 @@
 
   hard_regs_live_known = live_known;
 
   static_reload_reg_p = reload_reg_p;
 
 
 
+ZIP_DEBUG_LINE("Find reloads\n", insn);
 
+
 
   /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
 
      neither are insns that SET cc0.  Insns that use CC0 are not allowed
 
      to have any input reloads.  */
 
@@ -2707,8 +2718,17 @@
     no_output_reloads = 1;
     no_output_reloads = 1;
 
 
 #ifdef HAVE_cc0
 #ifdef HAVE_cc0
+  // If the instruction depends upon cc0, such as a branch, if_then_else, or
+  // If the instruction depends upon cc0, such as a branch, if_then_else, or
+  // cond_exec instruction, we cannot change the input so that the instruction
+  // cond_exec instruction, we cannot change the input so that the instruction

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.