OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Diff between revs 192 and 200

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 192 Rev 200
Line 136... Line 136...
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+
+
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-11-03 13:52:45.187664099 -0400
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
@@ -21,7 +21,7 @@
@@ -21,7 +21,7 @@
 #ifndef GCC_AARCH64_LINUX_H
 #ifndef GCC_AARCH64_LINUX_H
 #define GCC_AARCH64_LINUX_H
 #define GCC_AARCH64_LINUX_H
 
 
Line 148... Line 148...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
 
 
 #undef  ASAN_CC1_SPEC
 #undef  ASAN_CC1_SPEC
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
@@ -23,8 +23,8 @@
@@ -23,8 +23,8 @@
 #define EXTRA_SPECS \
 #define EXTRA_SPECS \
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
 
 
Line 162... Line 162...
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif DEFAULT_LIBC == LIBC_GLIBC
 #elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
@@ -68,8 +68,8 @@
@@ -68,8 +68,8 @@
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
 
 
 #undef  GLIBC_DYNAMIC_LINKER
 #undef  GLIBC_DYNAMIC_LINKER
Line 176... Line 176...
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
 
 
 #define GLIBC_DYNAMIC_LINKER \
 #define GLIBC_DYNAMIC_LINKER \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
@@ -62,7 +62,7 @@
@@ -62,7 +62,7 @@
 
 
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
 
 
Line 188... Line 188...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
    %{static:-Bstatic} \
    %{static:-Bstatic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -45,7 +45,7 @@
@@ -45,7 +45,7 @@
   %{shared:-G -Bdynamic} \
   %{shared:-G -Bdynamic} \
   %{!shared: %{!static: \
   %{!shared: %{!static: \
    %{rdynamic:-export-dynamic} \
    %{rdynamic:-export-dynamic} \
Line 200... Line 200...
+   -dynamic-linker /lib/ld-uClibc.so.0} \
+   -dynamic-linker /lib/ld-uClibc.so.0} \
    %{static}} -init __init -fini __fini"
    %{static}} -init __init -fini __fini"
 
 
 #undef TARGET_SUPPORTS_SYNC_CALLS
 #undef TARGET_SUPPORTS_SYNC_CALLS
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -102,7 +102,7 @@
@@ -102,7 +102,7 @@
 #undef CRIS_DEFAULT_CPU_VERSION
 #undef CRIS_DEFAULT_CPU_VERSION
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 
 
Line 212... Line 212...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef CRIS_LINK_SUBTARGET_SPEC
 #undef CRIS_LINK_SUBTARGET_SPEC
 #define CRIS_LINK_SUBTARGET_SPEC \
 #define CRIS_LINK_SUBTARGET_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
@@ -129,9 +129,9 @@
@@ -129,9 +129,9 @@
 #endif
 #endif
 
 
 #if FBSD_MAJOR < 6
 #if FBSD_MAJOR < 6
Line 227... Line 227...
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
 #endif
 #endif
 
 
 /* NOTE: The freebsd-spec.h header is included also for various
 /* NOTE: The freebsd-spec.h header is included also for various
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
@@ -34,7 +34,7 @@
@@ -34,7 +34,7 @@
 #define ENDFILE_SPEC \
 #define ENDFILE_SPEC \
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
 
 
Line 239... Line 239...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-11-28 18:14:19.382586425 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -22,7 +22,7 @@
@@ -22,7 +22,7 @@
 #define GNU_USER_LINK_EMULATION "elf_i386"
 #define GNU_USER_LINK_EMULATION "elf_i386"
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
Line 251... Line 251...
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
 
 
 #undef STARTFILE_SPEC
 #undef STARTFILE_SPEC
 #if defined HAVE_LD_PIE
 #if defined HAVE_LD_PIE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
@@ -22,6 +22,6 @@
@@ -22,6 +22,6 @@
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
 
 
Line 264... Line 264...
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
@@ -19,4 +19,4 @@
@@ -19,4 +19,4 @@
 <http://www.gnu.org/licenses/>.  */
 <http://www.gnu.org/licenses/>.  */
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
@@ -27,6 +27,6 @@
@@ -27,6 +27,6 @@
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
 
 
Line 286... Line 286...
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -20,4 +20,4 @@
@@ -20,4 +20,4 @@
 <http://www.gnu.org/licenses/>.  */
 <http://www.gnu.org/licenses/>.  */
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386"
 #define GNU_USER_LINK_EMULATION "elf_i386"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -55,7 +55,7 @@
@@ -55,7 +55,7 @@
 /* Define this for shared library support because it isn't in the main
 /* Define this for shared library support because it isn't in the main
    linux.h file.  */
    linux.h file.  */
 
 
Line 307... Line 307...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
@@ -32,4 +32,4 @@
@@ -32,4 +32,4 @@
 
 
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -31,5 +31,4 @@
@@ -31,5 +31,4 @@
   while (0)
   while (0)
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 #undef GNU_USER_DYNAMIC_LINKER
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
-
-
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
--- gcc-5.3.0-original/gcc/config/linux.h       2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/linux.h       2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
@@ -73,10 +73,10 @@
@@ -73,10 +73,10 @@
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
    supporting both 32-bit and 64-bit compilation.  */
    supporting both 32-bit and 64-bit compilation.  */
Line 344... Line 344...
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
@@ -67,7 +67,7 @@
@@ -67,7 +67,7 @@
    %{shared:-shared} \
    %{shared:-shared} \
    %{symbolic:-Bsymbolic} \
    %{symbolic:-Bsymbolic} \
    %{rdynamic:-export-dynamic} \
    %{rdynamic:-export-dynamic} \
Line 356... Line 356...
+   -dynamic-linker /lib/ld-linux.so.2"
+   -dynamic-linker /lib/ld-linux.so.2"
 
 
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -71,7 +71,7 @@
@@ -71,7 +71,7 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 368... Line 368...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "-m m68kelf %{shared} \
 #define LINK_SPEC "-m m68kelf %{shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
@@ -28,7 +28,7 @@
@@ -28,7 +28,7 @@
 #undef TLS_NEEDS_GOT
 #undef TLS_NEEDS_GOT
 #define TLS_NEEDS_GOT 1
 #define TLS_NEEDS_GOT 1
 
 
Line 380... Line 380...
+#define DYNAMIC_LINKER "/lib/ld.so.1"
+#define DYNAMIC_LINKER "/lib/ld.so.1"
 #undef  SUBTARGET_EXTRA_SPECS
 #undef  SUBTARGET_EXTRA_SPECS
 #define SUBTARGET_EXTRA_SPECS \
 #define SUBTARGET_EXTRA_SPECS \
   { "dynamic_linker", DYNAMIC_LINKER }
   { "dynamic_linker", DYNAMIC_LINKER }
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
@@ -22,20 +22,20 @@
@@ -22,20 +22,20 @@
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
 
 
 #define GLIBC_DYNAMIC_LINKER32 \
 #define GLIBC_DYNAMIC_LINKER32 \
Line 410... Line 410...
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
 
 
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
 #define GNU_USER_DYNAMIC_LINKERN32 \
 #define GNU_USER_DYNAMIC_LINKERN32 \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
@@ -32,7 +32,7 @@
@@ -32,7 +32,7 @@
 #undef  ASM_SPEC
 #undef  ASM_SPEC
 #define ASM_SPEC ""
 #define ASM_SPEC ""
 
 
Line 422... Line 422...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
@@ -37,7 +37,7 @@
@@ -37,7 +37,7 @@
 /* Define this for shared library support because it isn't in the main
 /* Define this for shared library support because it isn't in the main
    linux.h file.  */
    linux.h file.  */
 
 
Line 434... Line 434...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 #undef LINK_SPEC
 #undef LINK_SPEC
 #define LINK_SPEC "\
 #define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
@@ -357,14 +357,14 @@
@@ -357,14 +357,14 @@
 #undef LINK_OS_DEFAULT_SPEC
 #undef LINK_OS_DEFAULT_SPEC
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 
 
Line 457... Line 457...
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif DEFAULT_LIBC == LIBC_GLIBC
 #elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
@@ -757,8 +757,8 @@
@@ -757,8 +757,8 @@
 
 
 #define LINK_START_LINUX_SPEC ""
 #define LINK_START_LINUX_SPEC ""
 
 
Line 471... Line 471...
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #if DEFAULT_LIBC == LIBC_UCLIBC
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
@@ -60,8 +60,8 @@
@@ -60,8 +60,8 @@
 #define MULTILIB_DEFAULTS { "m31" }
 #define MULTILIB_DEFAULTS { "m31" }
 #endif
 #endif
 
 
Line 485... Line 485...
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC \
 #define LINK_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-11-03 13:52:45.203663997 -0400
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -43,7 +43,7 @@
@@ -43,7 +43,7 @@
 
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
 
Line 497... Line 497...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #undef SUBTARGET_LINK_EMUL_SUFFIX
 #undef SUBTARGET_LINK_EMUL_SUFFIX
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-11-03 13:52:45.207663972 -0400
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
@@ -84,8 +84,8 @@
@@ -84,8 +84,8 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 520... Line 520...
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
   %{!shared: \
   %{!shared: \
     %{!static: \
     %{!static: \
       %{rdynamic:-export-dynamic} \
       %{rdynamic:-export-dynamic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-11-03 13:52:45.207663972 -0400
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
@@ -83,7 +83,7 @@
@@ -83,7 +83,7 @@
    When the -shared link option is used a final link is not being
    When the -shared link option is used a final link is not being
    done.  */
    done.  */
 
 
Line 532... Line 532...
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 #undef  LINK_SPEC
 #undef  LINK_SPEC
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-11-03 13:52:45.207663972 -0400
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
@@ -41,7 +41,7 @@
@@ -41,7 +41,7 @@
   %{!shared: \
   %{!shared: \
     %{!static: \
     %{!static: \
       %{rdynamic:-export-dynamic} \
       %{rdynamic:-export-dynamic} \
Line 544... Line 544...
+      -dynamic-linker /lib/ld.so.1} \
+      -dynamic-linker /lib/ld.so.1} \
     %{static:-static}}"
     %{static:-static}}"
 
 
 #undef  WCHAR_TYPE
 #undef  WCHAR_TYPE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-11-03 13:52:45.207663972 -0400
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-11-28 18:14:19.386586394 -0500
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
@@ -44,7 +44,7 @@
@@ -44,7 +44,7 @@
   %{mlongcalls:--longcalls} \
   %{mlongcalls:--longcalls} \
   %{mno-longcalls:--no-longcalls}"
   %{mno-longcalls:--no-longcalls}"
 
 
Line 704... Line 704...
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-11-02 10:55:10.906812219 -0400
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-11-19 08:28:56.703678695 -0500
@@ -0,0 +1,2291 @@
@@ -0,0 +1,2293 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   zip.c
+// Filename:   zip.c
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 792... Line 792...
+#include "tm-preds.h"
+#include "tm-preds.h"
+
+
+#include "diagnostic.h"
+#include "diagnostic.h"
+// #include "integrate.h"
+// #include "integrate.h"
+
+
 
+#include "zip-protos.h"
 
+
+// static int  zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
+// static int  zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
+// static      bool    zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
+// static      bool    zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
+static bool    zip_return_in_memory(const_tree, const_tree);
+static bool    zip_return_in_memory(const_tree, const_tree);
+static bool    zip_frame_pointer_required(void);
+static bool    zip_frame_pointer_required(void);
+
+
Line 1262... Line 1264...
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+               if (dbg)  fprintf(stderr, "sp_fp_offset is %d\n", cfun->machine->sp_fp_offset);
+               if (dbg)  fprintf(stderr, "sp_fp_offset is %d\n", cfun->machine->sp_fp_offset);
+       }
+       }
+}
+}
+
+
+bool
+int
+zip_use_return_insn(void)
+zip_use_return_insn(void)
+{
+{
+       if ((!reload_completed)||(cfun->machine->fp_needed)
+       if ((!reload_completed)||(cfun->machine->fp_needed)
+                       ||(get_frame_size()!=0)) {
+                       ||(get_frame_size()!=0)) {
+               // If R0 ever gets pushed to the stack, then we cannot
+               // If R0 ever gets pushed to the stack, then we cannot
+               // use a master return from anywhere.  We need to clean up the
+               // use a master return from anywhere.  We need to clean up the
+               // stack first.
+               // stack first.
+               if ((!crtl->is_leaf)||((df_regs_ever_live_p(0))
+               if ((!crtl->is_leaf)||((df_regs_ever_live_p(0))
+                                               &&(!call_used_regs[0]))) {
+                                               &&(!call_used_regs[0]))) {
+                       return false;
+                       return 0;
+               }
+               }
+       }
+       }
+       zip_compute_frame();
+       zip_compute_frame();
+       return (cfun->machine->size_for_adjusting_sp == 0);
+       return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
+}
+}
+
+
+/* As per the notes in M68k.c, quote the function epilogue should not depend
+/* As per the notes in M68k.c, quote the function epilogue should not depend
+ * upon the current stack pointer.  It should use the frame poitner only,
+ * upon the current stack pointer.  It should use the frame poitner only,
+ * if there is a frame pointer.  This is mandatory because of alloca; we also
+ * if there is a frame pointer.  This is mandatory because of alloca; we also
Line 2664... Line 2666...
+                       return NULL;
+                       return NULL;
+       } return result;
+       } return result;
+}
+}
+*/
+*/
+
+
+bool
+int
+zip_supported_condition(int c) {
+zip_supported_condition(int c) {
+       switch(c) {
+       switch(c) {
+       case NE: case LT: case EQ: case GT: case GE: case LTU:
+       case NE: case LT: case EQ: case GT: case GE: case LTU:
+               return true;
+               return 1;
+               break;
+               break;
+       default:
+       default:
+               break;
+               break;
+       } return false;
+       } return 0;
+}
+}
+
+
+bool
+bool
+zip_signed_comparison(int c) {
+zip_signed_comparison(int c) {
+       switch(c) {
+       switch(c) {
Line 2685... Line 2687...
+       default:
+       default:
+               break;
+               break;
+       } return false;
+       } return false;
+}
+}
+
+
+bool
+int
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
+       rtx_insn *insn;
+       rtx_insn *insn;
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
+       if (dbg) zip_debug_rtx_pfx("DST", dst);
+       if (dbg) zip_debug_rtx_pfx("DST", dst);
Line 2775... Line 2777...
+               if (dbg) {
+               if (dbg) {
+               fprintf(stderr, "ZIP::MOVSICC -- Unsupported condition: ");
+               fprintf(stderr, "ZIP::MOVSICC -- Unsupported condition: ");
+                       zip_debug_ccode(cmpcode);
+                       zip_debug_ccode(cmpcode);
+                       fprintf(stderr, "\n");
+                       fprintf(stderr, "\n");
+               }
+               }
+               return false;
+               return 0;
+       }
+       }
+       gcc_assert(zip_supported_condition((int)cmpcode));
+       gcc_assert(zip_supported_condition((int)cmpcode));
+
+
+       //; Always do the default move
+       //; Always do the default move
+       bool    conditionally_do_false = false;
+       bool    conditionally_do_false = false;
Line 2791... Line 2793...
+               if (dbg) {
+               if (dbg) {
+                       fprintf(stderr, "ZIP::MOVSICC -- Cant support the reverse condition: ");
+                       fprintf(stderr, "ZIP::MOVSICC -- Cant support the reverse condition: ");
+                       zip_debug_ccode(cmpcode);
+                       zip_debug_ccode(cmpcode);
+                       fprintf(stderr, "\n");
+                       fprintf(stderr, "\n");
+               }
+               }
+               return false;
+               return 0;
+       }
+       }
+
+
+       if ((!rtx_equal_p(dst, iffalse))&&(!conditionally_do_false)) {
+       if ((!rtx_equal_p(dst, iffalse))&&(!conditionally_do_false)) {
+               if (dbg)
+               if (dbg)
+               fprintf(stderr, "ZIP::MOVSICC -- EMITTING MOVE FALSE->DST\n");
+               fprintf(stderr, "ZIP::MOVSICC -- EMITTING MOVE FALSE->DST\n");
Line 2827... Line 2829...
+                       NULL_RTX, NULL_RTX), iffalse, dst));
+                       NULL_RTX, NULL_RTX), iffalse, dst));
+               if (dbg) zip_debug_rtx_pfx("BARE-F: ", insn);
+               if (dbg) zip_debug_rtx_pfx("BARE-F: ", insn);
+       }
+       }
+
+
+       // Return true on success
+       // Return true on success
+       return true;
+       return 1;
+}
+}
+
+
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
+       // We know upon entry that REG_P(dst) must be true
+       // We know upon entry that REG_P(dst) must be true
+       if (!REG_P(dst))
+       if (!REG_P(dst))
Line 2997... Line 2999...
+}
+}
+
+
+int    zip_is_conditional(rtx_insn *insn) {
+int    zip_is_conditional(rtx_insn *insn) {
+       return (get_attr_conditional(insn)==CONDITIONAL_YES);
+       return (get_attr_conditional(insn)==CONDITIONAL_YES);
+}
+}
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-float.md gcc-5.3.0-zip/gcc/config/zip/zip-float.md
 
--- gcc-5.3.0-original/gcc/config/zip/zip-float.md      1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/config/zip/zip-float.md   2016-11-10 10:17:53.248750791 -0500
 
@@ -0,0 +1,138 @@
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Filename:   zip-float.md
 
+;;
 
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
 
+;;
 
+;; Purpose:    This is the machine description of the ZipCPU floating point
 
+;;             unit (if installed).
 
+;;
 
+;;
 
+;; Creator:    Dan Gisselquist, Ph.D.
 
+;;             Gisselquist Technology, LLC
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Copyright (C) 2015, Gisselquist Technology, LLC
 
+;;
 
+;; This program is free software (firmware): you can redistribute it and/or
 
+;; modify it under the terms of  the GNU General Public License as published
 
+;; by the Free Software Foundation, either version 3 of the License, or (at
 
+;; your option) any later version.
 
+;;
 
+;; This program is distributed in the hope that it will be useful, but WITHOUT
 
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
 
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
+;; for more details.
 
+;;
 
+;; License:    GPL, v3, as defined and found on www.gnu.org,
 
+;;             http://www.gnu.org/licenses/gpl.html
 
+;;
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;;
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Floating point Op-codes
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+(define_insn "addsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPADD  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "subsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPSUB  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "mulsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPMUL  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "divsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (div:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPDIV  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+; (define_insn "floatsisf2"
 
+;      [(set (match_operand:SF 0 "register_operand" "=r"
 
+;              (float:SI (match_operand:SF 1 "register_operand" "r"))))
 
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
 
+;      "(ZIP_FPU)"
 
+;      "FPI2F  %1,%0")
 
+; (define_insn "floatunssisf2" ... ?)
 
+; (define_insn "fix_truncsfsi2"
 
+;      [(set (match_operand:SI 0 "register_operand" "=r"
 
+;              (float:SF (match_operand:SF 1 "register_operand" "r"))))
 
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
 
+;      "(ZIP_FPU)"
 
+;      "FPI2F  %1,%0")
 
+; (define_insn "nearbyintsf2" ... ?)
 
+; (define_insn "truncsfsi2" ... ?)
 
+(define_expand "negsf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
 
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
 
+                               gen_int_mode(1,SImode)));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+(define_expand "abssf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0],
 
+                               gen_int_mode(-2,SImode)));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+;
 
+;
 
+; STILL MISSING:
 
+;
 
+;
 
+;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-09-13 13:46:17.890711238 -0400
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-11-19 08:26:58.092386679 -0500
@@ -0,0 +1,4095 @@
@@ -0,0 +1,4096 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   gcc/config/zip/zip.h
+// Filename:   gcc/config/zip/zip.h
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 3051... Line 3195...
+#define        ZIP_MULTIPLY    1       // Assume we have multiply instructions
+#define        ZIP_MULTIPLY    1       // Assume we have multiply instructions
+#define        ZIP_DIVIDE      1       // Assume we have divide instructions
+#define        ZIP_DIVIDE      1       // Assume we have divide instructions
+#define        ZIP_FPU         0        // Assume we have no floating point instructions
+#define        ZIP_FPU         0        // Assume we have no floating point instructions
+#define        ZIP_PIPELINED   1       // Assume our instructions are pipelined
+#define        ZIP_PIPELINED   1       // Assume our instructions are pipelined
+#define        ZIP_VLIW        1       // Assume we have the VLIW feature
+#define        ZIP_VLIW        1       // Assume we have the VLIW feature
+#define        ZIP_ATOMIC      ((ZIP_PIPELINED)&&(ZIP_VLIW))
+#define        ZIP_ATOMIC      (ZIP_PIPELINED)
+#define        ZIP_PIC         0        // Attempting to produce PIC code, with GOT
+#define        ZIP_PIC         0        // Attempting to produce PIC code, with GOT
+#define        ZIP_HAS_DI      1
+#define        ZIP_HAS_DI      1
+// Should we use the peephole optimizations?
+// Should we use the peephole optimizations?
+#define        ZIP_PEEPHOLE    1       // 0 means no peephole optimizations.
+#define        ZIP_PEEPHOLE    1       // 0 means no peephole optimizations.
+// How about the new long multiply instruction set?
+// How about the new long multiply instruction set?
+#define        ZIP_LONGMPY     1       // 0 means use the old instruction set
+#define        ZIP_LONGMPY     1       // 0 means use the old instruction set
 
+#define        ZIP_NEW_CONDITION_CODE  0        // 0 means use the old condition codes
+
+
+// Zip has 16 registers in each user mode.
+// Zip has 16 registers in each user mode.
+//     Register 15 is the program counter (PC)
+//     Register 15 is the program counter (PC)
+//     Register 14 is the condition codes (CC)
+//     Register 14 is the condition codes (CC)
+//     Register 13 is the stack pointer   (SP)
+//     Register 13 is the stack pointer   (SP)
Line 3589... Line 3734...
+#undef LONG_LONG_TYPE_SIZE
+#undef LONG_LONG_TYPE_SIZE
+//
+//
+#define        CHAR_TYPE_SIZE  32
+#define        CHAR_TYPE_SIZE  32
+#define        SHORT_TYPE_SIZE 32
+#define        SHORT_TYPE_SIZE 32
+#define        INT_TYPE_SIZE   32
+#define        INT_TYPE_SIZE   32
+#define        LONG_TYPE_SIZE  32
+#define        LONG_TYPE_SIZE  64
+#define        LONG_LONG_TYPE_SIZE     64
+#define        LONG_LONG_TYPE_SIZE     64
+// BOOL_TYPE_SIZE defaults to CHAR_TYPE_SIZE
+// BOOL_TYPE_SIZE defaults to CHAR_TYPE_SIZE
+#undef FLOAT_TYPE_SIZE
+#undef FLOAT_TYPE_SIZE
+#undef DOUBLE_TYPE_SIZE
+#undef DOUBLE_TYPE_SIZE
+#undef LONG_DOUBLE_TYPE_SIZE
+#undef LONG_DOUBLE_TYPE_SIZE
+#define        FLOAT_TYPE_SIZE         32
+#define        FLOAT_TYPE_SIZE         32
+#define        DOUBLE_TYPE_SIZE        FLOAT_TYPE_SIZE // Zip CPU doesn't support dbls
+#define        DOUBLE_TYPE_SIZE        64      // This'll need to be done via emulation
+#define        LONG_DOUBLE_TYPE_SIZE   64      // This'll need to be done via emulation
+#define        LONG_DOUBLE_TYPE_SIZE   64      // This'll need to be done via emulation
+// SHORT_FRAC_TYPE_SIZE
+// SHORT_FRAC_TYPE_SIZE
+// LONG_FFRACT_TYPE_SIZE
+// LONG_FFRACT_TYPE_SIZE
+// LONG_LONG_FRACT_TIME_SIZE
+// LONG_LONG_FRACT_TIME_SIZE
+#undef SHORT_ACCUM_TYPE_SIZE
+#undef SHORT_ACCUM_TYPE_SIZE
Line 7092... Line 7237...
+#define        HImode  SImode
+#define        HImode  SImode
+#define        QAmode  SAmode
+#define        QAmode  SAmode
+#define        HAmode  SAmode
+#define        HAmode  SAmode
+
+
+#include "insn-modes.h"
+#include "insn-modes.h"
+#include "zip-protos.h"
+// #include "zip-protos.h"     // Cant include this here!
+
+
+#endif /* GCC_ZIP_H */
+#endif /* GCC_ZIP_H */
+
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-11-02 12:05:18.838341497 -0400
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-11-28 18:12:19.339493020 -0500
@@ -0,0 +1,3468 @@
@@ -0,0 +1,3058 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+;; Filename:   zip.md
+;; Filename:   zip.md
+;;
+;;
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
Line 7196... Line 7341...
+   (PC_REG             15)
+   (PC_REG             15)
+  ])
+  ])
+;
+;
+;
+;
+;
+;
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
+;; Predicates
+;; Predicates
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
+(define_predicate "zip_const_address_operand_p"
+(define_predicate "zip_const_address_operand_p"
+       (match_code "symbol_ref,const,label_ref,code_label")
+       (match_code "symbol_ref,const,label_ref,code_label")
+{
+{
+       return zip_const_address_operand(op);
+       return zip_const_address_operand(op);
+})
+})
Line 7282... Line 7433...
+       else if (CONST_INT_P(op))
+       else if (CONST_INT_P(op))
+               return 1;
+               return 1;
+       return 1;
+       return 1;
+})
+})
+
+
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
+;; Constraints
+;; Constraints
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
+;
+;
+(define_memory_constraint "S"
+(define_memory_constraint "S"
+       "Any memory referenced by a constant address, possibly unknown at compile time"
+       "Any memory referenced by a constant address, possibly unknown at compile time"
+       (and (match_code "mem")
+       (and (match_code "mem")
+               (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
+               (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
Line 7302... Line 7462...
+       "Any constant address, to include those made by symbols unknown at compile time"
+       "Any constant address, to include those made by symbols unknown at compile time"
+       (and (match_code "label_ref,code_label,symbol_ref,const")
+       (and (match_code "label_ref,code_label,symbol_ref,const")
+               (match_test "zip_ct_const_address_operand(op)")))
+               (match_test "zip_ct_const_address_operand(op)")))
+;
+;
+;
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
+;; Attributes
+;; Attributes
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+;
+;
+;
+(define_attr "predicable"  "no,yes" (const_string "yes"))
+(define_attr "predicable"  "no,yes" (const_string "yes"))
+(define_attr "conditional" "no,yes" (const_string "no"))
+(define_attr "conditional" "no,yes" (const_string "no"))
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
+;
+;
Line 7316... Line 7485...
+(define_mode_iterator ZI [SI])
+(define_mode_iterator ZI [SI])
+(define_mode_attr zipa [(SI "")])
+(define_mode_attr zipa [(SI "")])
+;
+;
+;
+;
+;
+;
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Instructions
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
+;; Instructions
+;; Instructions
+;
+;
+; (define_insn
+; (define_insn
+;      optional name
+;      optional name
+;      RTL template -- a vector of incomplete RTL expressions describing the
+;      RTL template -- a vector of incomplete RTL expressions describing the
Line 7349... Line 7529...
+;
+;
+;
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+;; Move instructions: both
+;; Move instructions: both
+;      (arbitrary) from variables to variables, but this gets
+;;     (arbitrary) from variables to variables, but this gets
+;              expanded into:
+;;             expanded into:
+;      from registers to registers
+;;     from registers to registers
+;      from immediates to registers
+;;     from immediates to registers
+;;
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+;
+;
+;
+;
+;
Line 7681... Line 7861...
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       ""
+       ""
+       "SUB    %3+%2,%0"
+       "SUB    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "mul<mode>3_oldstyle"
 
+       [(set (match_operand:ZI 0 "register_operand" "=r")
 
+               (mult:ZI (match_operand:ZI 1 "register_operand" "%r")
 
+                       (match_operand:ZI 2 "register_operand" "r")))
 
+       (clobber (match_scratch:ZI 3 "=r"))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
 
+       "(!ZIP_LONGMPY)"
 
+       "MOV    %1,%0
 
+       MPYS    %2,%0
 
+       MOV     %1,%3
 
+       ROL     16,%3
 
+       MPYS    %2,%3
 
+       ROL     16,%3
 
+       AND     0x0ffff,%3
 
+       ADD     %3,%0
 
+       MOV     %2,%3
 
+       ROL     16,%3
 
+       MPYS    %1,%3
 
+       ROL     16,%3
 
+       AND     0x0ffff,%3
 
+       ADD     %3,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+;
+;
+;
+;
+(define_expand "mul<mode>3"
+(define_expand "mul<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
Line 7777... Line 7934...
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI (mult:DI
+           (truncate:SI (ashiftrt:DI (mult:DI
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
+               (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
+               (const_int 32))))]
+               (const_int 32))))]
+       "(ZIP_LONGMPY)")
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))")
+(define_insn_and_split "smulsi3_highpart_split_reg"
+(define_insn_and_split "smulsi3_highpart_split_reg"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI (mult:DI
+           (truncate:SI (ashiftrt:DI (mult:DI
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (const_int 32))))]
+               (const_int 32))))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "#"
+       "#"
+       "(reload_completed)"
+       "(reload_completed)"
+       [(parallel [(set (match_dup 0)
+       [(parallel [(set (match_dup 0)
+               (truncate:SI (ashiftrt:DI
+               (truncate:SI (ashiftrt:DI
+                       (mult:DI
+                       (mult:DI
Line 7804... Line 7961...
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (sign_extend:DI
+               (sign_extend:DI
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+                       (const_int 32))))]
+                       (const_int 32))))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "#"
+       "#"
+       "(reload_completed)"
+       "(reload_completed)"
+       [(parallel [(set (match_dup 0)
+       [(parallel [(set (match_dup 0)
+               (truncate:SI (ashiftrt:DI
+               (truncate:SI (ashiftrt:DI
+                       (mult:SI
+                       (mult:SI
Line 7825... Line 7982...
+               (mult:SI
+               (mult:SI
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                 (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+                 (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (const_int 32))))
+               (const_int 32))))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%2,%0"
+       "MPYSHI\t%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "smulsi3_highpart_reg_raw"
+(define_insn "smulsi3_highpart_reg_raw"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI
+           (truncate:SI (ashiftrt:DI
+               (mult:SI
+               (mult:SI
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                 (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+                 (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (const_int 32))))
+               (const_int 32))))
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%2,%0"
+       "MPYSHI\t%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "smulsi3_highpart_off_raw"
+(define_insn "smulsi3_highpart_off_raw"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI
+           (truncate:SI (ashiftrt:DI
Line 7849... Line 8006...
+                 (sign_extend:DI (plus:SI
+                 (sign_extend:DI (plus:SI
+                               (match_operand:SI 2 "register_operand" "r")
+                               (match_operand:SI 2 "register_operand" "r")
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+               (const_int 32))))
+               (const_int 32))))
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%3+%2,%0"
+       "MPYSHI\t%3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "smulsi3_highpart_off_clobber"
+(define_insn "smulsi3_highpart_off_clobber"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI
+           (truncate:SI (ashiftrt:DI
Line 7862... Line 8019...
+                 (sign_extend:DI (plus:SI
+                 (sign_extend:DI (plus:SI
+                       (match_operand:SI 2 "register_operand" "r")
+                       (match_operand:SI 2 "register_operand" "r")
+                       (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+                       (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+               (const_int 32))))
+               (const_int 32))))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%3+%2,%0"
+       "MPYSHI\t%3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
+(define_expand "umulsi3_highpart"
+(define_expand "umulsi3_highpart"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI (mult:DI
+           (truncate:SI (ashiftrt:DI (mult:DI
+               (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
+               (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
+               (const_int 32))))]
+               (const_int 32))))]
+       "(ZIP_LONGMPY)")
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))")
+(define_insn_and_split "umulsi3_highpart_split_reg"
+(define_insn_and_split "umulsi3_highpart_split_reg"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI (mult:DI
+           (truncate:SI (ashiftrt:DI (mult:DI
+               (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+               (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (const_int 32))))]
+               (const_int 32))))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "#"
+       "#"
+       "(reload_completed)"
+       "(reload_completed)"
+       [(parallel [(set (match_dup 0)
+       [(parallel [(set (match_dup 0)
+               (truncate:SI (ashiftrt:DI
+               (truncate:SI (ashiftrt:DI
+                       (mult:SI
+                       (mult:SI
Line 7901... Line 8058...
+                 (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                 (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                 (zero_extend:DI
+                 (zero_extend:DI
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
+               (const_int 32))))]
+               (const_int 32))))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "#"
+       "#"
+       "(reload_completed)"
+       "(reload_completed)"
+       [(parallel [(set (match_dup 0)
+       [(parallel [(set (match_dup 0)
+               (truncate:SI (ashiftrt:DI
+               (truncate:SI (ashiftrt:DI
+                       (mult:DI
+                       (mult:DI
Line 7922... Line 8079...
+               (mult:DI
+               (mult:DI
+                   (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                   (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                   (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+                   (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (const_int 32))))
+               (const_int 32))))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%2,%0"
+       "MPYSHI\t%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "umulsi3_highpart_reg_raw"
+(define_insn "umulsi3_highpart_reg_raw"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI
+           (truncate:SI (ashiftrt:DI
+               (mult:DI
+               (mult:DI
+                  (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                  (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+                  (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+                  (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
+               (const_int 32))))
+               (const_int 32))))
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%2,%0"
+       "MPYSHI\t%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "umulsi3_highpart_off_raw"
+(define_insn "umulsi3_highpart_off_raw"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI
+           (truncate:SI (ashiftrt:DI
Line 7946... Line 8103...
+                   (zero_extend:DI (plus:SI
+                   (zero_extend:DI (plus:SI
+                               (match_operand:SI 2 "register_operand" "r")
+                               (match_operand:SI 2 "register_operand" "r")
+                               (match_operand:DI 3 "zip_opb_immv_p" "N"))))
+                               (match_operand:DI 3 "zip_opb_immv_p" "N"))))
+               (const_int 32))))
+               (const_int 32))))
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%3+%2,%0"
+       "MPYSHI\t%3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+(define_insn "umulsi3_highpart_off_clobber"
+(define_insn "umulsi3_highpart_off_clobber"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+           (truncate:SI (ashiftrt:DI
+           (truncate:SI (ashiftrt:DI
Line 7959... Line 8116...
+                   (zero_extend:DI (plus:SI
+                   (zero_extend:DI (plus:SI
+                       (match_operand:SI 2 "register_operand" "r")
+                       (match_operand:SI 2 "register_operand" "r")
+                       (match_operand:DI 3 "zip_opb_immv_p" "N"))))
+                       (match_operand:DI 3 "zip_opb_immv_p" "N"))))
+               (const_int 32))))
+               (const_int 32))))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       "(ZIP_LONGMPY)"
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
+       "MPYSHI\t%3+%2,%0"
+       "MPYSHI\t%3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
+(define_expand "div<mode>3"
+(define_expand "div<mode>3"
Line 8056... Line 8213...
+       "CMP    %0,%2
+       "CMP    %0,%2
+       MOV.LT  %2,%0"
+       MOV.LT  %2,%0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+;
+;
 
+; AND
 
+;
 
+;
+(define_expand "and<mode>3"
+(define_expand "and<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+(define_insn_and_split "and<mode>3_reg_split"
+(define_insn_and_split "and<mode>3_reg_split"
Line 8120... Line 8280...
+       ""
+       ""
+       "AND    %3+%2,%0"
+       "AND    %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
 
+;
 
+;
 
+; iOR
 
+;
 
+;
+(define_expand "ior<mode>3"
+(define_expand "ior<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+(define_insn_and_split "ior<mode>3_reg_split"
+(define_insn_and_split "ior<mode>3_reg_split"
Line 8185... Line 8350...
+       "OR     %3+%2,%0"
+       "OR     %3+%2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
+;
+;
 
+;
 
+; XOR
 
+;
 
+;
 
+;
+(define_expand "xor<mode>3"
+(define_expand "xor<mode>3"
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
Line 8277... Line 8447...
+;;     BC      %3
+;;     BC      %3
+;;
+;;
+;; (define_insn "umulvsi4"
+;; (define_insn "umulvsi4"
+;;     ... ???)
+;;     ... ???)
+;;
+;;
 
+;
 
+;
 
+; ASR
 
+;
 
+;
+(define_expand "ashr<mode>3"
+(define_expand "ashr<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
+(define_insn_and_split "ashr<mode>3_split"
+(define_insn_and_split "ashr<mode>3_split"
Line 8310... Line 8485...
+       ""
+       ""
+       "ASR    %2,%0"
+       "ASR    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
 
+;
 
+; LSL
 
+;
 
+;
 
+;
+(define_expand "ashl<mode>3"
+(define_expand "ashl<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
+(define_insn_and_split "ashl<mode>3_split"
+(define_insn_and_split "ashl<mode>3_split"
Line 8343... Line 8523...
+       ""
+       ""
+       "LSL    %2,%0"
+       "LSL    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
 
+;
 
+; LSR
 
+;
 
+;
 
+;
+(define_expand "lshr<mode>3"
+(define_expand "lshr<mode>3"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
+(define_insn_and_split "lshr<mode>3_split"
+(define_insn_and_split "lshr<mode>3_split"
Line 8410... Line 8595...
+       "ROL    %2,%0"
+       "ROL    %2,%0"
+       [(set_attr "ccresult" "set")])
+       [(set_attr "ccresult" "set")])
+;
+;
+;
+;
+;
+;
 
+;
 
+;
 
+; Others:  NEG, TEST, POPC, NOT
 
+;
 
+;
+(define_insn "neg<mode>2"
+(define_insn "neg<mode>2"
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+       [(set (match_operand:ZI 0 "register_operand" "=r")
+               (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
+               (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       ""
+       ""
Line 8462... Line 8652...
+;
+;
+;
+;
+;
+;
+(define_expand "movdi3"
+(define_expand "movdi3"
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
+               (match_operand:DI 1 "general_operand" ""))])
+               (match_operand:DI 1 "general_operand" ""))]
 
+       "(ZIP_HAS_DI)")
+(define_insn "movdi_lod"
+(define_insn "movdi_lod"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))]
+               (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))]
+       ""
+       "(ZIP_HAS_DI)"
+       {
+       {
+               if (REG_P(operands[1]))
+               if (REG_P(operands[1]))
+                       return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
+                       return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
+               else if (GET_CODE(operands[1])==PLUS) {
+               else if (GET_CODE(operands[1])==PLUS) {
+                       if ((REG_P(XEXP(operands[1],0)))
+                       if ((REG_P(XEXP(operands[1],0)))
Line 8486... Line 8677...
+       }
+       }
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "movdi_sto"
+(define_insn "movdi_sto"
+       [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
+       [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
+               (match_operand:DI 1 "register_operand" "r"))]
+               (match_operand:DI 1 "register_operand" "r"))]
+       ""
+       "(ZIP_HAS_DI)"
+       {
+       {
+               if (REG_P(operands[0]))
+               if (REG_P(operands[0]))
+                       return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
+                       return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
+               else if (GET_CODE(operands[0])==PLUS) {
+               else if (GET_CODE(operands[0])==PLUS) {
+                       if ((REG_P(XEXP(operands[0],0)))
+                       if ((REG_P(XEXP(operands[0],0)))
Line 8506... Line 8697...
+       }
+       }
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "movdi_ldi"
+(define_insn "movdi_ldi"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (match_operand:DI 1 "immediate_operand" "i"))]
+               (match_operand:DI 1 "immediate_operand" "i"))]
+       ""
+       "(ZIP_HAS_DI)"
+       "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
+       "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
 
+;
 
+;
 
+; ADD
 
+;
 
+;
+(define_insn "adddi3" ; Fastest/best instruction always goes first
+(define_insn "adddi3" ; Fastest/best instruction always goes first
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
 
+;
 
+;
 
+; SUB
 
+;
 
+;
+(define_insn "subdi3"
+(define_insn "subdi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
 
+;
 
+;
 
+; AND
 
+;
 
+;
+(define_insn "anddi3"
+(define_insn "anddi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "AND    %L2,%L0\n\tAND\t%H2,%H0"
+       "AND    %L2,%L0\n\tAND\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
 
+;
 
+;
 
+; iOR
 
+;
 
+;
+(define_insn "iordi3"
+(define_insn "iordi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "OR     %2,%0\n\tOR\t%H2,%H0"
+       "OR     %L2,%L0\n\tOR\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
 
+;
 
+;
 
+; XOR
 
+;
 
+;
+(define_insn "xordi3"
+(define_insn "xordi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "XOR    %2,%0\n\tXOR\t%H2,%H0"
+       "XOR    %L2,%L0\n\tXOR\t%H2,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
 
+;
 
+;
 
+; NEG
 
+;
 
+;
+(define_insn "negdi2"
+(define_insn "negdi2"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "XOR    -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
+       "XOR    -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
+(define_insn "absdi2"
+;
+       [(set (match_operand:DI 0 "register_operand" "=r")
+;
 
+; ABS
 
+;
 
+;
 
+(define_insn "absdi2"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (abs:DI (match_operand:DI 1 "register_operand" "0")))
+               (abs:DI (match_operand:DI 1 "register_operand" "0")))
+       (clobber (match_scratch:SI 2 "=r"))
+       (clobber (match_scratch:SI 2 "=r"))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "CLR    %2
+       "CLR    %2
+       TEST    %H0             ; Problem, we can't tell conditions
+       TEST    %H0             ; Problem, we can't tell conditions
+       LDILO.LT        1,%2
+       LDILO.LT        1,%2
+       XOR.LT  -1,%L0
+       XOR.LT  -1,%L0
+       XOR.LT  -1,%H0
+       XOR.LT  -1,%H0
+       ADD     %2,%L0
+       ADD     %2,%L0
+       ADD.C   1,%H0"
+       ADD.C   1,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; NOT
 
+;
 
+;
+(define_insn "one_cmpldi2"
+(define_insn "one_cmpldi2"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "XOR    -1,%L0\n\tXOR\t-1,%H0"
+       "XOR    -1,%L0\n\tXOR\t-1,%H0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; Unsigned min/max
 
+;
 
+;
+(define_insn "umindi3"
+(define_insn "umindi3"
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "CMP    %H0,%H2
+       "CMP    %H0,%H2
+       CMP.Z   %L0,%L2
+       CMP.Z   %L0,%L2
+       MOV.C   %H2,%H0
+       MOV.C   %H2,%H0
+       MOV.C   %L2,%L0"
+       MOV.C   %L2,%L0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
Line 8609... Line 8845...
+       [(set (match_operand:DI 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "register_operand" "=r")
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
+                       (match_operand:DI 2 "register_operand" "r")))
+                       (match_operand:DI 2 "register_operand" "r")))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "CMP    %H2,%H0
+       "CMP    %H2,%H0
+       CMP.Z   %L2,%L0
+       CMP.Z   %L2,%L0
+       MOV.C   %H2,%H0
+       MOV.C   %H2,%H0
+       MOV.C   %L2,%L0"
+       MOV.C   %L2,%L0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; POP
 
+;
 
+;
+(define_insn "popcountdi2"
+(define_insn "popcountdi2"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (popcount:SI (match_operand:DI 1 "register_operand" "r")))
+               (popcount:SI (match_operand:DI 1 "register_operand" "r")))
+       (clobber (match_scratch:SI 2 "=r"))
+       (clobber (match_scratch:SI 2 "=r"))
+       (clobber (reg:CC CC_REG))
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       "POPC   %L1,%0
+       "POPC   %L1,%0
+       POPC    %H1,%2
+       POPC    %H1,%2
+       ADD     %2,%0"
+       ADD     %2,%0"
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
 
+;
 
+;
 
+; PARITY
 
+;
 
+;
+(define_expand "paritydi2"
+(define_expand "paritydi2"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+       [(set (match_operand:SI 0 "register_operand" "=r")
+               (popcount (match_operand:DI 1 "register_operand" "r")))
+               (popcount (match_operand:DI 1 "register_operand" "r")))
+       (set (match_dup 0) (and:SI (match_dup 0) (const_int -2)))
+       (set (match_dup 0) (and:SI (match_dup 0) (const_int -2)))
+       ])
+       ])
+;(define_insn "extendsidi2"
+;(define_insn "extendsidi2"
+;      [(set (match_operand:DI 0 "register_operand" "=r")
+;      [(set (match_operand:DI 0 "register_operand" "=r")
+;              (sign_extend:DI (match_operand:SI 0 "register_operand" "r")))]
+;              (sign_extend:DI (match_operand:SI 0 "register_operand" "r")))]
+;      ""
+;      "(ZIP_HAS_DI)"
+;      "TEST\t%1\nMOV\t%1,%L0\nCLR\t%L1\nLDI.LT\t-1,%L1"
+;      "TEST\t%1\nMOV\t%1,%L0\nCLR\t%L1\nLDI.LT\t-1,%L1"
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;(define_insn "mulsidi3"
+;(define_insn "mulsidi3"
+;      [(set (match_operand:DI 0 "register_operand" "=r")
+;      [(set (match_operand:DI 0 "register_operand" "=r")
+;              (mult:SI (match_operand:SI 1 "register_operand" "%r")
+;              (mult:SI (match_operand:SI 1 "register_operand" "%r")
+;                      (match_operand:SI 2 "register_operand" "r")))
+;                      (match_operand:SI 2 "register_operand" "r")))
+;      (clobber (match_scratch:SI 3 "=r"))]
+;      (clobber (match_scratch:SI 3 "=r"))]
+;      ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
+;      ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
+;      ""
+;      "(ZIP_HAS_DI)"
+;      "MOV    %1,%L0
+;      "MOV    %1,%L0
+;      MPYS    %2,%L0                  ; L0 = R2 * R1
+;      MPYS    %2,%L0                  ; L0 = R2 * R1
+;      MOV     %1,%3                   ; R3 = R1
+;      MOV     %1,%3                   ; R3 = R1
+;      ROL     16,%3                   ; R3 = (R1 <<< 16)
+;      ROL     16,%3                   ; R3 = (R1 <<< 16)
+;      MPYS    %2,%3                   ; R3 = (R1 <<< 16) * R2
+;      MPYS    %2,%3                   ; R3 = (R1 <<< 16) * R2
Line 8691... Line 8937...
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
+                       [(match_operand:DI 2 "register_operand" "r")
+                       [(match_operand:DI 2 "register_operand" "r")
+                               (match_operand:DI 3 "register_operand" "r")])
+                               (match_operand:DI 3 "register_operand" "r")])
+                       (const_int 1) (const_int 0)))
+                       (const_int 1) (const_int 0)))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       ""
+       "(ZIP_HAS_DI)"
+       {
+       {
+               switch(GET_CODE(operands[1])) {
+               switch(GET_CODE(operands[1])) {
+               case EQ:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
+               case EQ:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
+               case NE:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
+               case NE:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
+               case LTU:       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
+               case LTU:       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
+               case LEU:       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
+               case LEU:
 
+                       if (ZIP_NEW_CONDITION_CODE)
 
+                       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.NC\t1,%0\n";
 
+                       else
 
+                       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
+               case GTU:       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
+               case GTU:       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
+               case GEU:       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
+               case GEU:
 
+                       if (ZIP_NEW_CONDITION_CODE)
 
+                       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NC\t1,%0\n";
 
+                       else
 
+                       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
+               default:
+               default:
+                       gcc_unreachable();
+                       gcc_unreachable();
+               }
+               }
+       }
+       }
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
Line 8807... Line 9061...
+       [(gt (reg:CC CC_REG) (const_int 0))]
+       [(gt (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
+       "(GT)"
+       "(GT)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+(define_cond_exec
+(define_cond_exec
 
+       [(geu (reg:CC CC_REG) (const_int 0))]
 
+       "(ZIP_NEW_CONDITION_CODE)"
 
+       "(NC)"
 
+       [(set_attr "conditional" "yes")])
 
+(define_cond_exec
+       [(ge (reg:CC CC_REG) (const_int 0))]
+       [(ge (reg:CC CC_REG) (const_int 0))]
+       ""
+       "(!ZIP_NEW_CONDITION_CODE)"
+       "(GE)"
+       "(GE)"
+       [(set_attr "conditional" "yes")])
+       [(set_attr "conditional" "yes")])
+(define_cond_exec
+(define_cond_exec
+       [(ltu (reg:CC CC_REG) (const_int 0))]
+       [(ltu (reg:CC CC_REG) (const_int 0))]
+       ""
+       ""
Line 9019... Line 9278...
+;;     Op 0 = the comparison operator (le,lt,eq,ne,gt,ge,and usgn ltu,geu,etc.)
+;;     Op 0 = the comparison operator (le,lt,eq,ne,gt,ge,and usgn ltu,geu,etc.)
+;;     Op 1&2 the operands of the compare instruction
+;;     Op 1&2 the operands of the compare instruction
+;;     Op 3 is the jump label
+;;     Op 3 is the jump label
+;;
+;;
+;;
+;;
+;; #warning Need to adjust this so that the "LT" code doesnt get generated ...
 
+;;
+;;
+(define_expand "cbranch<mode>4"
+(define_expand "cbranch<mode>4"
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r")
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r")
+               (match_operand:ZI 2 "zip_opb_operand_p" "rO")))
+               (match_operand:ZI 2 "zip_opb_operand_p" "rO")))
+       (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
+       (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
Line 9048... Line 9306...
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       DONE;
+                       DONE;
+               } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
+               } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
+                       //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
+                       //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
 
+                       if (ZIP_NEW_CONDITION_CODE) {
 
+                               emit_insn(gen_cmpsi(operands[1], operands[2]));
 
+                               emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
 
+                       } else {
+                       emit_insn(gen_cmpsi_off(operands[2], operands[1],
+                       emit_insn(gen_cmpsi_off(operands[2], operands[1],
+                                       GEN_INT(1)));
+                                       GEN_INT(1)));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
 
+                       }
+                       DONE;
+                       DONE;
+               } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
+               } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
+                       //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
+                       //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
+                       //; Swap operands, turn into a GTE compare
+                       //; Swap operands, turn into a GTE compare
 
+                       if (ZIP_NEW_CONDITION_CODE) {
 
+                               emit_insn(gen_cmpsi_off(operands[1], operands[2],
 
+                                       GEN_INT(1)));
 
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
 
+                       } else {
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
+                       emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
+                       emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
 
+                       }
+                       DONE;
+                       DONE;
+               } // ; Otherwise ... just handle the branch normally
+               } // ; Otherwise ... just handle the branch normally
+
+
+               //; Except ... we can do better for some instructions, such as
+               //; Except ... we can do better for some instructions, such as
+               //; LE.  While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
+               //; LE.  While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
Line 9092... Line 9361...
+                                               XEXP(operands[2],0),
+                                               XEXP(operands[2],0),
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
+                               DONE;
+                               DONE;
+                       }
+                       }
 
+#if (ZIP_NEW_CONDITION_CODE != 0)
 
+               } else if (GET_CODE(operands[0])==GE) {
 
+                       if ((CONST_INT_P(operands[2]))
 
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
 
+                               //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
 
+                               emit_insn(gen_cmpsi(operands[1],
 
+                                               GEN_INT(INTVAL(operands[2])+1)));
 
+                               emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
 
+                               DONE;
 
+                       //; Now for the controversial ones--where we add one
 
+                       //; when it may or may not be permissable.  For now, we
 
+                       //; just do it anyway and postpone the philosophical
 
+                       //; discussion for later.
 
+                       } else if (REG_P(operands[2])) {
 
+                               emit_insn(gen_cmpsi_off(operands[1],
 
+                                               operands[2],GEN_INT(1)));
 
+                               emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
 
+                               DONE;
 
+                       } else if ((GET_CODE(operands[2])==PLUS)
 
+                               &&(REG_P(XEXP(operands[2],0)))
 
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
 
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
 
+                               emit_insn(gen_cmpsi_off(operands[1],
 
+                                               XEXP(operands[2],0),
 
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
 
+                               emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
 
+                               DONE;
 
+                       }
 
+#endif
+               } else if (GET_CODE(operands[0])==LEU) {
+               } else if (GET_CODE(operands[0])==LEU) {
 
+#if (ZIP_NEW_CONDITION_CODE != 0)
 
+                       emit_insn(gen_cmpsi(operands[1], operands[2]));
 
+                       emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
 
+#else
+                       if ((CONST_INT_P(operands[2]))
+                       if ((CONST_INT_P(operands[2]))
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
+                               //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
+                               //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
+                               emit_insn(gen_cmpsi(operands[1],
+                               emit_insn(gen_cmpsi(operands[1],
+                                               GEN_INT(INTVAL(operands[2])+1)));
+                                               GEN_INT(INTVAL(operands[2])+1)));
Line 9117... Line 9419...
+                                       XEXP(operands[2],0),
+                                       XEXP(operands[2],0),
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+                               DONE;
+                               DONE;
+                       }
+                       }
 
+#endif
+               }}
+               }}
+       })
+       })
+(define_insn "cbranch_jmp_eq"
+(define_insn "cbranch_jmp_eq"
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
Line 9165... Line 9468...
+       ""
+       ""
+       "BGT\t%0"
+       "BGT\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_ge"
+(define_expand "cbranch_jmp_ge"
 
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
 
+                (label_ref (match_operand 0 "" ""))
 
+                (pc)))])
 
+(define_insn "cbranch_jmp_ge_newcc"
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))]
+                (pc)))]
+       ""
+       "(ZIP_NEW_CONDITION_CODE)"
 
+       "BGT\t%0\n\tBZ\t%0"
 
+       [(set_attr "predicable" "no")
 
+               (set_attr "conditional" "yes")
 
+               (set_attr "ccresult" "unchanged")])
 
+(define_insn "cbranch_jmp_ge_oldcc"
 
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
 
+                (label_ref (match_operand 0 "" ""))
 
+                (pc)))]
 
+       "(!ZIP_NEW_CONDITION_CODE)"
+       "BGE\t%0"
+       "BGE\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_ltu"
+(define_insn "cbranch_jmp_ltu"
Line 9183... Line 9499...
+       ""
+       ""
+       "BC\t%0"
+       "BC\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_gtu"
+(define_expand "cbranch_jmp_gtu"
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))
+                (pc)))])
+       ;(clobber (reg:CC CC_REG))
+(define_insn "cbranch_jmp_gtu_newcc"
+       ]
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
+       ""      ; Flip the condition, and then we can jump
+                (label_ref (match_operand 0 "" ""))
 
+                (pc)))]
 
+       "(ZIP_NEW_CONDITION_CODE)"
 
+       ;// We could flip the condition code, and then be able to jump.
 
+       ;// The problem is that doing this adjusts the condition code, and
 
+       ;// we aren't allowed to do that here.
 
+       ;//
 
+       ;// The problem here is the equals.  What do you do if A=B?  Our new
 
+       ;// condition tests for A>=B, not A>B.  So ... how do you get rid of
 
+       ;// the equals?  We do so here by branching around. (sigh)
 
+       "BZ\t.Lgtu%=\n\tBNC\t%0\n.Lgtu%=:"
 
+       [(set_attr "predicable" "no")
 
+               (set_attr "conditional" "yes")
 
+               (set_attr "ccresult" "unknown")])
 
+(define_insn "cbranch_jmp_gtu_oldcc"
 
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
 
+                (label_ref (match_operand 0 "" ""))
 
+                (pc)))]
 
+       "(!ZIP_NEW_CONDITION_CODE)"
 
+       ;// We could flip the condition code, and then be able to jump.
 
+       ;// The problem is that doing this adjusts the condition code, and
 
+       ;// we aren't allowed to do that here.
 
+       ;//
 
+       ;// With the old condition code, things are worse.  Sure, we still need
 
+       ;// to branch around, but it's worse 'cause we are always branching
 
+       ;// around the conditional branch.  With the new condition code, we
 
+       ;// only branch around on part of the unsupported condition.
+       "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:"
+       "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unknown")])
+               (set_attr "ccresult" "unknown")])
+(define_insn "cbranch_jmp_leu"
+(define_insn "cbranch_jmp_leu"
Line 9204... Line 9546...
+       "BC\t%0
+       "BC\t%0
+       BZ\t%0"
+       BZ\t%0"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unchanged")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranch_jmp_geu"
+(define_expand "cbranch_jmp_geu"
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
+                (label_ref (match_operand 0 "" ""))
+                (label_ref (match_operand 0 "" ""))
+                (pc)))
+                (pc)))])
+       ;(clobber (reg:CC CC_REG))
+(define_insn "cbranch_jmp_geu_newcc"
+       ]
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
+       ""
+                (label_ref (match_operand 0 "" ""))
 
+                (pc)))]
 
+       "(ZIP_NEW_CONDITION_CODE)"
 
+       "BNC\t%0"
 
+       [(set_attr "predicable" "no")
 
+               (set_attr "conditional" "yes")
 
+               (set_attr "ccresult" "unchanged")])
 
+(define_insn "cbranch_jmp_geu_oldcc"
 
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
 
+                (label_ref (match_operand 0 "" ""))
 
+                (pc)))]
 
+       "(!ZIP_NEW_CONDITION_CODE)"
+       "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:"
+       "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:"
+       [(set_attr "predicable" "no")
+       [(set_attr "predicable" "no")
+               (set_attr "conditional" "yes")
+               (set_attr "conditional" "yes")
+               (set_attr "ccresult" "unknown")])
+               (set_attr "ccresult" "unchanged")])
+(define_insn "cbranchdi4"
+(define_insn "cbranchdi4"
+       [(set (pc) (if_then_else
+       [(set (pc) (if_then_else
+               (match_operator 0 "ordered_comparison_operator"
+               (match_operator 0 "ordered_comparison_operator"
+                       [(match_operand:DI 1 "register_operand" "r")
+                       [(match_operand:DI 1 "register_operand" "r")
+                               (match_operand:DI 2 "register_operand" "r")])
+                               (match_operand:DI 2 "register_operand" "r")])
+                       (label_ref (match_operand 3 "" ""))
+                       (label_ref (match_operand 3 "" ""))
+                       (pc)))
+                       (pc)))
+       (clobber (reg:CC CC_REG))]
+       (clobber (reg:CC CC_REG))]
+       ""
+       "(ZIP_HAS_DI)"
+       {
+       {
+               switch(GET_CODE(operands[0])) {
+               switch(GET_CODE(operands[0])) {
+               case EQ:
+               case EQ:
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
+               case NE:
+               case NE:
+                       return "CMP\t%H2,%H1\n\tCMP.NZ\t%L2,%L1\n\tBNZ\t%3";
+                       return "CMP\t%H2,%H1\n\tCMP.NZ\t%L2,%L1\n\tBNZ\t%3";
+               case LE:
+               case LE:
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
+                       if (ZIP_NEW_CONDITION_CODE)
 
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBNC\t%3\n.Ldi%=:";
 
+                       else
 
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3\n.Ldi%=";
+               case GT:
+               case GT:
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
+               case LT:
+               case LT:
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n.Ldi%=:";
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n.Ldi%=:";
+               case GE:
+               case GE:
 
+                       if (ZIP_NEW_CONDITION_CODE)
 
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBNC\t%3\n.Ldi%=:";
 
+                       else
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\nBZ\t%3\n.Ldi%=:";
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\nBZ\t%3\n.Ldi%=:";
+               case LTU:
+               case LTU:
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n";
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n";
+               case LEU:
+               case LEU:
 
+                       if (ZIP_NEW_CONDITION_CODE)
 
+                       return "CMP\t%H1,%H2\n\tBC\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBNC\t%3\n.Ldi%=:";
 
+                       else
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
+               case GTU:
+               case GTU:
+                       return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\n";
+                       return "CMP\t%H1,%H2\n\tBC\t%3\nBNZ\t%.Ldi%=\nCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
+               case GEU:
+               case GEU:
 
+                       if (ZIP_NEW_CONDITION_CODE)
 
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBNC\t%3";
 
+                       else
+                       return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\nBZ\t%3";
+                       return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\nBZ\t%3";
+               default:
+               default:
+                       gcc_unreachable();
+                       gcc_unreachable();
+               }
+               }
+       }
+       }
Line 9606... Line 9971...
+       ; "JMP  R0"
+       ; "JMP  R0"
+       ; [(set_attr "ccresult" "unchanged")])
+       ; [(set_attr "ccresult" "unchanged")])
+(define_insn "*return" ; A "*" -- means it cannot be called from C
+(define_insn "*return" ; A "*" -- means it cannot be called from C
+       [(return)]
+       [(return)]
+       ""
+       ""
+       "JMP    R0"
+       "RETN"
+       [(set_attr "ccresult" "unchanged")])
+       [(set_attr "ccresult" "unchanged")])
+(define_insn "simple_return"   ; A "*" -- means it cannot be called from C
+(define_insn "simple_return"   ; A "*" -- means it cannot be called from C
+       [(simple_return)]
+       [(simple_return)]
+       ""
+       ""
+       "JMP    R0"
+       "RETN"
+       [(set_attr "ccresult" "unchanged")])
+       [(set_attr "ccresult" "unchanged")])
+(define_insn "return_if_eq"
+(define_insn "return_if_eq"
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
+                       (return) (pc)))]
+                       (return) (pc)))]
+       "zip_use_return_insn()"
+       "zip_use_return_insn()"
+       "JMP.Z  R0"
+       "RETN.Z"
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+(define_insn "return_if_ne"
+(define_insn "return_if_ne"
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
+                       (return) (pc)))]
+                       (return) (pc)))]
+       "zip_use_return_insn()"
+       "zip_use_return_insn()"
+       "JMP.NZ R0"
+       "RETN.NZ"
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+(define_insn "return_if_lt"
+(define_insn "return_if_lt"
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
+                       (return) (pc)))]
+                       (return) (pc)))]
+       "zip_use_return_insn()"
+       "zip_use_return_insn()"
+       "JMP.LT R0"
+       "RETN.LT"
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+(define_insn "return_if_gt"
+(define_insn "return_if_gt"
+       [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
+                       (return) (pc)))]
+                       (return) (pc)))]
+       "zip_use_return_insn()"
+       "zip_use_return_insn()"
+       "JMP.GT R0"
+       "RETN.GT"
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
 
+;(define_insn "return_if_gte"
 
+       ;[(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
 
+                       ;(return) (pc)))]
 
+       ;"((ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
 
+       ;"RETN.GT\n\tRETN.Z"
 
+       ;[(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+(define_insn "return_if_gte"
+(define_insn "return_if_gte"
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
+                       (return) (pc)))]
+                       (return) (pc)))]
+       "zip_use_return_insn()"
+       "((!ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
+       "JMP.GTE        R0"
+       "RETN.GTE"
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+(define_insn "return_if_ltu"
+(define_insn "return_if_ltu"
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
+                       (return) (pc)))]
+                       (return) (pc)))]
+       "zip_use_return_insn()"
+       "zip_use_return_insn()"
+       "JMP.C  R0"
+       "RETN.C"
 
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
 
+(define_insn "return_if_geu"
 
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
 
+                       (return) (pc)))]
 
+       "((ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
 
+       "RETN.NC"
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
+;
+;
+;
+;
+;
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;
Line 9835... Line 10212...
+; number placed into this is not constant, or how to specify that it must *only*
+; number placed into this is not constant, or how to specify that it must *only*
+; be constant.  Thats actually the problem with both proposals, zip_break(id)
+; be constant.  Thats actually the problem with both proposals, zip_break(id)
+; and zip_reg(regno)--both depend upon a compile time constant to work.
+; and zip_reg(regno)--both depend upon a compile time constant to work.
+;
+;
+;
+;
+
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Floating point Op-codes
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+(define_insn "addsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPADD  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "subsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPSUB  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "mulsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPMUL  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "divsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (div:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPDIV  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_expand "negsf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
 
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
 
+                               gen_int_mode(1,SImode)));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+(define_expand "abssf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0],
 
+                               gen_int_mode(-2,SImode)));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+;
+;
+;
+;
+;
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
Line 9962... Line 10255...
+       "BREAK\t%1"
+       "BREAK\t%1"
+       [(set_attr "predicable" "no")])
+       [(set_attr "predicable" "no")])
+;
+;
+;
+;
+;
+;
 
+;
 
+(include "zip-float.md")
 
+(include "zip-sync.md")
 
+(include "zip-peephole.md")
 
+;
 
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+;; Unimplemented (or not yet implemented) RTL Codes
+;; Unimplemented (or not yet implemented) RTL Codes
+;;
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+;
+;
+;
+;
+;
+;(define_insn "sync_compare_and_swapsi"
 
+;      [(set ...
 
+;              )]
 
+;      "(ZIP_ATMOC)"
 
+;      LOCK            (alu)           // Hmmm ... need to modify if I will
 
+;      LOD     %1,%0   OP-VALID        // operate on the value before the store
 
+;      CMP     %0,%2   DCD-valid
 
+;      STO.Z   %2,%1   PF-valid
 
+;
 
+;(define_insn "sync_lock_test_and_setsi"
 
+;      LOCK
 
+;      LOD     %1,%0
 
+;      STO     %0,%1
 
+;
 
+;(define_insn "sync_lock_releasesi"
 
+;      STO     %1,%0
 
+;
 
+;
+;
 
+;(define_insn "addvsi4"
 
+;      )
 
+;(define_insn "subvsi4"
 
+;      )
 
+;(define_insn "mulvsi4"
 
+;      )
 
+;(define_insn "umulvsi4"
 
+;      )
 
+;(define_insn "umulvsi4"
 
+;      )
+;(define_insn "negvsi3"
+;(define_insn "negvsi3"
+;      "MOV    %1,%0
+;      "MOV    %1,%0
+;      XOR     -1,%0
+;      XOR     -1,%0
+;      ADD     1,%0
+;      ADD     1,%0
+;      BV      %2"
+;      BV      %2"
+;      "")
+;      )
 
+;
 
+;(define_insn "ssum_widen
 
+;(define_insn "usum_widen
 
+;(define_insn "udot_prod"
 
+;(define_insn "maddsidi4"
 
+;(define_insn "umaddsidi4"
 
+;(define_insn "msubsidi4"
 
+;(define_insn "umsubsidi4"
 
+;
 
+;
 
+; STILL MISSING:
 
+;      SYSCALL(ID)
 
+;              MOV %ID,R0
 
+;              CLR     CC
 
+;      cmove   ... the conditional move, created from a
 
+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
 
+;      pattern
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
 
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def     1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def  2016-03-08 12:10:21.982586940 -0500
 
@@ -0,0 +1,23 @@
 
+/*
 
+ * Commends in C-long comment form
 
+ * class
 
+ *     Mode = "SI"
 
+ *     PRECISION, BYTESIZE, COUNT ??
 
+ *     FORMAT
 
+ *     EXPR
 
+ *
 
+ * The manual says I need to define BITS_PER_UNIT here.
 
+ */
 
+// INT_MODE(QI, 1);
 
+// INT_MODE(HI, 1);
 
+// INT_MODE(SI, 1);
 
+// INT_MODE(DI, 2);
 
+
 
+// FLOAT_MODE(SF, 1, ieee_single_format);
 
+// FLOAT_MODE(DF, 2, ieee_single_format);
 
+
 
+// We cannot override machmodes.def from here.  Thus, even though our QI,
 
+// HI, and SI modes are all 1-byte, we cant set them that way here.  The
 
+// change needed to be made in machmodes.def.  Hence, here is a target
 
+// configuration change--in machmodes.def--that properly belonged in the
 
+// config directory.
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-peephole.md gcc-5.3.0-zip/gcc/config/zip/zip-peephole.md
 
--- gcc-5.3.0-original/gcc/config/zip/zip-peephole.md   1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/config/zip/zip-peephole.md        2016-11-09 12:12:15.750820248 -0500
 
@@ -0,0 +1,617 @@
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Filename:   zip-peephole.md
 
+;;
 
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
 
+;;
 
+;; Purpose:    This is a machine description of a variety of peephole
 
+;;             optimizations which can be applied to the ZipCPU RTL
 
+;;     representation.
 
+;;
 
+;;
 
+;; Creator:    Dan Gisselquist, Ph.D.
 
+;;             Gisselquist Technology, LLC
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Copyright (C) 2015, Gisselquist Technology, LLC
 
+;;
 
+;; This program is free software (firmware): you can redistribute it and/or
 
+;; modify it under the terms of  the GNU General Public License as published
 
+;; by the Free Software Foundation, either version 3 of the License, or (at
 
+;; your option) any later version.
 
+;;
 
+;; This program is distributed in the hope that it will be useful, but WITHOUT
 
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
 
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
+;; for more details.
 
+;;
 
+;; License:    GPL, v3, as defined and found on www.gnu.org,
 
+;;             http://www.gnu.org/licenses/gpl.html
 
+;;
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Peephole optimizations
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+;
+;
+;
+; Match:
+; Match:
+;      CMP     R1,R0
+;      CMP     R1,R0
+;      BGTU    lbl
+;      BGTU    lbl
+; Transform to:
+; Transform to:
Line 10562... Line 10948...
+;      BRA target ; two branches to the same identical target in a row ...
+;      BRA target ; two branches to the same identical target in a row ...
+;
+;
+;
+;
+;
+;
+; STILL MISSING:
+; STILL MISSING:
+;      SYSCALL(ID)
+;
+;              MOV %ID,R0
+;
+;              CLR     CC
+;
+;      cmove   ... the conditional move, created from a
 
+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
 
+;      pattern
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
 
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def     1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def  2016-03-08 12:10:21.982586940 -0500
 
@@ -0,0 +1,23 @@
 
+/*
 
+ * Commends in C-long comment form
 
+ * class
 
+ *     Mode = "SI"
 
+ *     PRECISION, BYTESIZE, COUNT ??
 
+ *     FORMAT
 
+ *     EXPR
 
+ *
 
+ * The manual says I need to define BITS_PER_UNIT here.
 
+ */
 
+// INT_MODE(QI, 1);
 
+// INT_MODE(HI, 1);
 
+// INT_MODE(SI, 1);
 
+// INT_MODE(DI, 2);
 
+
 
+// FLOAT_MODE(SF, 1, ieee_single_format);
 
+// FLOAT_MODE(DF, 2, ieee_single_format);
 
+
 
+// We cannot override machmodes.def from here.  Thus, even though our QI,
 
+// HI, and SI modes are all 1-byte, we cant set them that way here.  The
 
+// change needed to be made in machmodes.def.  Hence, here is a target
 
+// configuration change--in machmodes.def--that properly belonged in the
 
+// config directory.
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-09-13 15:32:55.403521585 -0400
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-11-10 08:13:53.322577755 -0500
@@ -0,0 +1,81 @@
@@ -0,0 +1,80 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   zip-protos.h
+// Filename:   zip-protos.h
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 10637... Line 10993...
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+#ifndef        ZIP_PROTOS_H
+#ifndef        ZIP_PROTOS_H
+#define        ZIP_PROTOS_H
+#define        ZIP_PROTOS_H
+
+
+extern bool    zip_supported_condition(int c);
+extern int     zip_supported_condition(int c);
+extern void    zip_expand_prologue(void);
+extern void    zip_expand_prologue(void);
+extern void    zip_expand_epilogue(void);
+extern void    zip_expand_epilogue(void);
+extern void    zip_sibcall_epilogue(void);
+extern void    zip_sibcall_epilogue(void);
+extern bool    zip_expand_movsicc(rtx,rtx,rtx,rtx);
+extern int     zip_expand_movsicc(rtx,rtx,rtx,rtx);
+extern int     zip_initial_elimination_offset(int, int);
+extern int     zip_initial_elimination_offset(int, int);
+extern void    zip_print_operand(FILE *, rtx, int);
+extern void    zip_print_operand(FILE *, rtx, int);
+extern void    zip_print_operand_address(FILE *, rtx);
+extern void    zip_print_operand_address(FILE *, rtx);
+extern enum    reg_class       zip_reg_class(int);
+extern enum    reg_class       zip_reg_class(int);
+extern rtx     zip_return_addr_rtx(int, rtx);
+extern rtx     zip_return_addr_rtx(int, rtx);
Line 10655... Line 11011...
+
+
+extern void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
+extern void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
+extern bool    zip_function_ok_for_sibcall(tree, tree);
+extern bool    zip_function_ok_for_sibcall(tree, tree);
+extern int     zip_address_operand(rtx op);
+extern int     zip_address_operand(rtx op);
+extern int     zip_const_address_operand(rtx op);
+extern int     zip_const_address_operand(rtx op);
+extern bool    zip_gen_move_rtl(rtx, rtx);
+extern int     zip_use_return_insn(void);
+extern bool    zip_use_return_insn(void);
 
+extern const char *zip_set_zero_or_one(rtx, rtx);
+extern const char *zip_set_zero_or_one(rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+
+
+extern int     zip_insn_sets_cc(rtx_insn *insn);
+extern int     zip_insn_sets_cc(rtx_insn *insn);
+extern int     zip_is_conditional(rtx_insn *insn);
+extern int     zip_is_conditional(rtx_insn *insn);
Line 10680... Line 11035...
+extern void    zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
+extern void    zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
+extern void    zip_ifcvt_modify_insn(struct ce_if_block *ceinfo, rtx pattern, rtx_insn *insn);
+extern void    zip_ifcvt_modify_insn(struct ce_if_block *ceinfo, rtx pattern, rtx_insn *insn);
+
+
+#endif
+#endif
+
+
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-sync.md gcc-5.3.0-zip/gcc/config/zip/zip-sync.md
 
--- gcc-5.3.0-original/gcc/config/zip/zip-sync.md       1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/config/zip/zip-sync.md    2016-11-10 06:58:36.795045234 -0500
 
@@ -0,0 +1,303 @@
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Filename:   zip-sync.md
 
+;;
 
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
 
+;;
 
+;; Purpose:    This is that portion of the machine description of the Zip CPU
 
+;;             which is focused on atomic operations.
 
+;;
 
+;;
 
+;; Creator:    Dan Gisselquist, Ph.D.
 
+;;             Gisselquist Technology, LLC
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Copyright (C) 2015, Gisselquist Technology, LLC
 
+;;
 
+;; This program is free software (firmware): you can redistribute it and/or
 
+;; modify it under the terms of  the GNU General Public License as published
 
+;; by the Free Software Foundation, either version 3 of the License, or (at
 
+;; your option) any later version.
 
+;;
 
+;; This program is distributed in the hope that it will be useful, but WITHOUT
 
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
 
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
+;; for more details.
 
+;;
 
+;; License:    GPL, v3, as defined and found on www.gnu.org,
 
+;;             http://www.gnu.org/licenses/gpl.html
 
+;;
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;;
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Atomic access Op-codes
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+; First, the basic atomic_ operators, add, sub, ior, and, and xor
 
+;
 
+(define_insn "atomic_addsi"
 
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
 
+               (plus:SI (match_dup 0)
 
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
 
+       (const (match_operand 2 "" ""))         ; Memory model used
 
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %0,%3\n\tADD %1,%3\n\tSTO %3,%0\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_subsi"
 
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
 
+               (minus:SI (match_dup 0)
 
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
 
+       (const (match_operand 2 "" ""))         ; Memory model used
 
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %0,%3\n\tSUB %1,%3\n\tSTO %3,%0\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_iorsi"
 
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
 
+               (ior:SI (match_dup 0)
 
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
 
+       (const (match_operand 2 "" ""))         ; Memory model used
 
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %0,%3\n\tOR %1,%3\n\tSTO %3,%0\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_andsi"
 
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
 
+               (and:SI (match_dup 0)
 
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
 
+       (const (match_operand 2 "" ""))         ; Memory model used
 
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %0,%3\n\tAND %1,%3\n\tSTO %3,%0\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_xorsi"
 
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
 
+               (xor:SI (match_dup 0)
 
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
 
+       (const (match_operand 2 "" ""))         ; Memory model used
 
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %0,%3\n\tXOR %1,%3\n\tSTO %3,%0\n"
 
+       [(set_attr "predicable" "no")])
 
+;
 
+;
 
+; Given how the ZipCPU is put together, all LODs and STOs are atomic.  Hence,
 
+; we just expand these operators so that they can be used by the other already
 
+; existent LOD/STO RTL operators.
 
+;
 
+(define_expand "atomic_loadsi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_operand:SI 1 "zip_memory_operand_p" "Q"))])
 
+(define_expand "atomic_loaddi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_operand:SI 1 "zip_memory_operand_p" "Q"))])
 
+(define_expand "atomic_storesi"
 
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
 
+               (match_operand:DI 1 "register_operand" "r"))])
 
+(define_expand "atomic_storedi"
 
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
 
+               (match_operand:DI 1 "register_operand" "r"))])
 
+;
 
+;
 
+;
 
+;
 
+(define_insn "atomic_exchangesi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_operand:SI 1 "zip_memory_operand_p" "+Q"))
 
+       (set (match_dup 1) (match_operand:SI 2 "register_operand" "r"))
 
+       ; (match_operand 3 "" "")               ; Memory model used
 
+       ]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tSTO %2,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+;
 
+;
 
+;
 
+; Here's another set of the atomic operators, this time those that leave their
 
+; result in operand zero.
 
+;
 
+(define_insn "atomic_add_fetchsi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (plus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))
 
+       ; (match_operand 3 "" "")               ; Memory model used
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tADD %2,%0\n\tSTO %0,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_sub_fetchsi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (minus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tSUB %2,%0\n\tSTO %0,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_or_fetchsi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (ior:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (match_dup 1) (ior:SI (match_dup 1) (match_dup 2)))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tOR %2,%0\n\tSTO %0,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_and_fetchsi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (and:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (match_dup 1) (and:SI (match_dup 1) (match_dup 2)))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tAND %2,%0\n\tSTO %0,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_xor_fetchsi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (xor:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
 
+       (set (match_dup 1) (xor:SI (match_dup 1) (match_dup 2)))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tXOR %2,%0\n\tSTO %0,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+;
 
+;
 
+;
 
+;
 
+(define_insn "atomic_fetch_addsi"
 
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+               (plus:SI (match_dup 1)
 
+                       (match_operand:SI 2 "register_operand" "=r")))
 
+       (set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_dup 1))
 
+       (set (match_dup 2) (plus:SI (match_dup 1) (match_dup 2)))
 
+       ; (match_operand 3 "" "")               ; Memory model used
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tADD %0,%2\n\tSTO %2,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+;(define_insn "atomic_fetch_subsi"
 
+;      [(set (match_operand:SI 0 "register_operand" "=r")
 
+;              (minus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+;                      (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
 
+;      (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
 
+;      (clobber (reg:CC CC_REG))]
 
+;      "(ZIP_ATOMIC)"
 
+;
 
+; HERE WE HAVE A PROBLEM ... swapping the arguments does not work for a
 
+; subtract.  It creates the SUBR (subtract reverse) instruction, which is not
 
+; what the RTL names is supposed to capture.  Hence ... we cannot do this one.
 
+; If we could do two ALU instructions during the LOCK, then we might make
 
+; this work--but LOCK only provides for a single ALU instruction.
 
+;
 
+;      "LOCK\n\tLOD %1,%0\n\tSUB %2,%0\n\tSTO %0,%1\n"
 
+;      "LOCK\n\tLOD %1,%0\n\tSUB %0,%2\n\tSTO %2,%1\n"
 
+;      [(set_attr "predicable" "no")])
 
+(define_insn "atomic_fetch_orsi"
 
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+               (ior:SI (match_dup 1)
 
+                       (match_operand:SI 2 "register_operand" "=r")))
 
+       (set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_dup 1))
 
+       (set (match_dup 2) (ior:SI (match_dup 1) (match_dup 2)))
 
+       ; (match_operand 3 "" "")               ; Memory model used
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tOR %0,%2\n\tSTO %2,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_fetch_andsi"
 
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+               (and:SI (match_dup 1)
 
+                       (match_operand:SI 2 "register_operand" "=r")))
 
+       (set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_dup 1))
 
+       (set (match_dup 2) (and:SI (match_dup 1) (match_dup 2)))
 
+       ; (match_operand 3 "" "")               ; Memory model used
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tAND %0,%2\n\tSTO %2,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+(define_insn "atomic_fetch_xorsi"
 
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
 
+               (xor:SI (match_dup 1)
 
+                       (match_operand:SI 2 "register_operand" "=r")))
 
+       (set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_dup 1))
 
+       (set (match_dup 2) (xor:SI (match_dup 1) (match_dup 2)))
 
+       ; (match_operand 3 "" "")               ; Memory model used
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_ATOMIC)"
 
+       "LOCK\n\tLOD %1,%0\n\tXOR %0,%2\n\tSTO %2,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+;
 
+;
 
+;
 
+;
 
+(define_insn "atomic_test_and_set"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (match_operand:SI 1 "zip_memory_operand_p" "+Q"))
 
+       (set (match_dup 1)
 
+               (if_then_else
 
+                       (eq (match_dup 1)
 
+                               (const_int 0))
 
+                       (const_int 1)
 
+                       (match_dup 1)))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))
 
+       (set (match_scratch:SI 3) (const_int 1))
 
+       (const (match_operand 2 "" ""))]        ; Memory model used
 
+       "(ZIP_ATOMIC)"
 
+       "LDI    1,%3
 
+       LOCK
 
+       LOD     %1,%0
 
+       TST     %0
 
+       STO.Z   %3,%1\n"
 
+       [(set_attr "predicable" "no")])
 
+;
 
+;
 
+;
 
+(define_insn "atomic_compare_and_swapsi"
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (if_then_else
 
+                       (eq (match_operand:SI 2 "zip_memory_operand_p" "+Q")
 
+                               (match_operand:SI 3 "zip_opb_single_operand_p" "rO"))
 
+                       (const_int 1)
 
+                       (const_int 0)))
 
+       (set (match_operand:SI 1 "register_operand" "=r") (match_dup 2))
 
+       (set (match_dup 2) (if_then_else
 
+                       (eq (match_dup 2) (match_dup 3))
 
+                               (match_operand:SI 4 "register_operand" "r")
 
+                               (match_dup 0)))]
 
+       "(ZIP_ATOMIC)"
 
+       "CLR %0
 
+       LOCK
 
+       LOD %2,%1
 
+       CMP %3,%1
 
+       STO.Z %4,%1
 
+       LDI.Z 1,%0"
 
+       [(set_attr "predicable" "no")])
 
+;
 
+;
 
+;
 
+;
 
+; STILL MISSING:
 
+;
 
+;      deprecated sync_* atomic functions
 
+;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
+++ gcc-5.3.0-zip/gcc/config.gcc        2016-02-14 00:53:37.389411987 -0500
+++ gcc-5.3.0-zip/gcc/config.gcc        2016-02-14 00:53:37.389411987 -0500
@@ -479,6 +479,10 @@
@@ -479,6 +479,10 @@
 tilepro*-*-*)
 tilepro*-*-*)
Line 11980... Line 12642...
              cselib_val *val = cselib_lookup_from_insn (mem, indmode, true,
              cselib_val *val = cselib_lookup_from_insn (mem, indmode, true,
                                                         VOIDmode,
                                                         VOIDmode,
                                                         get_insns ());
                                                         get_insns ());
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/config.host gcc-5.3.0-zip/libgcc/config.host
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/config.host gcc-5.3.0-zip/libgcc/config.host
--- gcc-5.3.0-original/libgcc/config.host       2015-10-01 08:01:18.000000000 -0400
--- gcc-5.3.0-original/libgcc/config.host       2015-10-01 08:01:18.000000000 -0400
+++ gcc-5.3.0-zip/libgcc/config.host    2016-01-30 15:16:00.459883558 -0500
+++ gcc-5.3.0-zip/libgcc/config.host    2016-11-10 07:09:05.510509734 -0500
@@ -195,6 +195,9 @@
@@ -195,6 +195,9 @@
 tic6x-*-*)
 tic6x-*-*)
        cpu_type=c6x
        cpu_type=c6x
        ;;
        ;;
+zip*)
+zip*)
+       cpu_type=zip
+       cpu_type=zip
+       ;;
+       ;;
 esac
 esac
 
 
 # Common parts for widely ported systems.
 # Common parts for widely ported systems.
@@ -1300,6 +1303,9 @@
@@ -1296,6 +1299,9 @@
        echo "*** Configuration ${host} not supported" 1>&2
        tmake_file="$tmake_file nvptx/t-nvptx"
        exit 1
        extra_parts="crt0.o"
        ;;
        ;;
+zip*)
+zip*)
+       tmake_file="${tmake_file} t-softfp-sfdf t-softfp"
+       tmake_file="${tmake_file} t-softfp-sfdf t-softfp"
+       ;;
+       ;;
 esac
 *)
 
        echo "*** Configuration ${host} not supported" 1>&2
 case ${host} in
        exit 1
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/libgcc2.h gcc-5.3.0-zip/libgcc/libgcc2.h
 
--- gcc-5.3.0-original/libgcc/libgcc2.h 2015-01-05 07:33:28.000000000 -0500
 
+++ gcc-5.3.0-zip/libgcc/libgcc2.h      2016-11-19 08:23:48.085519135 -0500
 
@@ -113,10 +113,10 @@
 
    because the sizes for those types can be configured to be anything.
 
    Instead we use the following special type names.  */
 
 
 
-typedef                 int QItype     __attribute__ ((mode (QI)));
 
-typedef unsigned int UQItype   __attribute__ ((mode (QI)));
 
-typedef                 int HItype     __attribute__ ((mode (HI)));
 
-typedef unsigned int UHItype   __attribute__ ((mode (HI)));
 
+typedef                 int QItype     __attribute__ ((mode (SI)));
 
+typedef unsigned int UQItype   __attribute__ ((mode (SI)));
 
+typedef                 int HItype     __attribute__ ((mode (SI)));
 
+typedef unsigned int UHItype   __attribute__ ((mode (SI)));
 
 #if MIN_UNITS_PER_WORD > 1
 
 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1.  */
 
 typedef         int SItype     __attribute__ ((mode (SI)));
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgomp/configure.tgt gcc-5.3.0-zip/libgomp/configure.tgt
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgomp/configure.tgt gcc-5.3.0-zip/libgomp/configure.tgt
--- gcc-5.3.0-original/libgomp/configure.tgt    2015-03-13 06:57:07.000000000 -0400
--- gcc-5.3.0-original/libgomp/configure.tgt    2015-03-13 06:57:07.000000000 -0400
+++ gcc-5.3.0-zip/libgomp/configure.tgt 2016-01-30 15:16:51.323521641 -0500
+++ gcc-5.3.0-zip/libgomp/configure.tgt 2016-01-30 15:16:51.323521641 -0500
@@ -150,6 +150,9 @@
@@ -150,6 +150,9 @@
        # Need to link with -lpthread so libgomp.so is self-contained.
        # Need to link with -lpthread so libgomp.so is self-contained.

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.